MPC821 datasheet(210/242 Pages) NXP

210 / 242 page

Support Information

MPC860TFADS Daughter Board Design Specification—Rev 0.1

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

114

BBVD2

O, X

Buffered PCMCIA slot A Battery Voltage Detect 2. In fact IP_A5.

Used in conjunction with BBVD1 to determine the battery status

of a PC-Card. In case of MPC823 or MPC850 daughter boards,

connected to IP_B5 signal of the MPC.

115

GND

116

117

N.C.

118

DP0

I/O

DP0/IRQ3~. Data Parity line 0 or Interrupt Request 3. May

generate and receive parity data for D(0:7) bits connected to the

DRAM SIMM. May not be conﬁgured as IRQ3~.

119

V3.3

120

DP2

I/O

DP2/IRQ5~. Data Parity line 2 or Interrupt Request 5. May

generate and receive parity data for D(16:23) bits connected to

the DRAM SIMM. May not be conﬁgured as IRQ5~.

121

V3.3

122

DP1

I/O

DP1/IRQ4~. Data Parity line1 or Interrupt Request 4. May

generate and receive parity data for D(8:15) bits connected to the

DRAM SIMM. May not be conﬁgured as IRQ4~.

123

V3.3

124

N.C.

125

V3.3

126

IRQ1~

I/O, L

Interrupt Request 1.Pulled-up but otherwise not used on the

FADS.

127

V3.3

128

SPARE3

I/O, X

MPC’s spare line 3. Pulled - up but otherwise unused on the

FADS.

129

V3.3

130

IRQ7~

I/O, L

Interrupt Request 7. The lowest priority interrupt request line.

Pulled - up but otherwise not used on the FADS.

131

V3.3

132

N.C.

133

V3.3

134

NMI~

I/O, L

Non-Makable Interrupt. In fact IRQ0~ of the MPC. Driven by on-

board logic by O.D. gate. Pulled - up. May be driven off-board by

O.D. gate only.

135

V3.3

136

N.C.

137

V3.3

TABLE 5-10. PM2 Interconnect Signals

Pin No.

Signal Name

Attribute

Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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