MPC821 datasheet(36/242 Pages) NXP

36 / 242 page

Functional Description

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

FIGURE 4-1 Refresh Scheme

As seen in FIGURE 4-1 "Refresh Scheme" above, the BRG clock is twice divided: once by the PTP

(Periodic Timer Prescaler) and again by another prescaler - the PTA, dedicated for each UPM. If

there are more than one dram banks, than refresh cycles are performed for consecutive banks, there-

fore, refresh should be made faster. The formula for calculation of the PTA is given below:

Where:

•

PTA - Periodic Timer A filed in MAMR. The value of the 2’nd divider.

•

Refresh_Period is the time (usually in msec) required to refresh a dram bank

•

Number_Of_Beats_Per_Refresh_Cycle: using the UPM looping capability, it is possible to

perform more than one refresh cycle per refresh burst (in fact upto 16).

•

Number_Of_Rows_To_Refresh: the number of rows in a dram bank

•

T_BRG: the cycle time of the BRG clock

•

MPTPR: the value of the periodic timer prescaler (2 to 64)

•

Number_Of_Banks: number of dram banks to refresh.

If we take for example a MCM36200 SIMM which has the following data:

•

Refresh_Period == 16 msec

•

Number_Of_Beats_Per_Refresh_Cycle: on the FADS it is 4.

•

Number_Of_Rows_To_Refresh == 1024

•

T_BRG == 20 nsec (system clock @ 50 Mhz)

•

MPTPR arbitrarily chosen to be 16

•

Number_Of_Banks == 2 for that SIMM

If we assign the figures to the PTA formula we get the value of PTA should be 97 decimal or 61 hex.

4•6•4

Variable Bus-Width Control

Since a port’s width determines its address lines’ connection scheme, i.e., the number of address

lines required for byte-selection varies (1 for 16-bit port and 2 for 32-bit port) according to the port’s

width, it is necessary to change address connections to a memory port if its width is to be changed.

E.g.: if a certain memory is initially configured as a 32-bit port, the list significant address line which

is connected to that memory’s A0 line should be the MPC’s A29. Now, if that port is to be reconfigured

as a 16-bit port, the LS address line becomes A30.

If a linearA address scheme is to be maintained, all address lines connected to that memory are to

A. Consequent addresses lead to adjacent memory cells

PTP

PTB

UPMB

DRAM BANKS

BRG Clock

PTA =

Refresh_Period X Number_Of_Beats_Per_Refresh_Cycle

Number_Of_Rows_To_Refresh X

X MPTPR X Number_Of_Banks

T_BRG

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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