MPC821 datasheet(26/242 Pages) NXP

26 / 242 page

OPERATING INSTRUCTIONS

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

a. BR3 is not initialized for MB321xx or MB324xx EDO DRAM SIMMs.

b. Assuming 16.67MHz BRGCLK

MAMR

MB321BT08TASN60

60A21114

refresh clock divided by 60, periodic timer enabled,

type 2 address multiplexing scheme, 1 cycle disable

timer, GPL4 disabled for data sampling edge ﬂexibility,

1 loop read, 1 loop write, 4 beats refresh burst.

MB322BT08TASN60

30A21114

refresh clock divided by 30, periodic timer

enabled, type 2 address multiplexing scheme, 1 cycle

disable timer, GPL4 disabled for data sampling edge

ﬂexibility, 1 loop read, 1 loop write, 4 beats refresh

burst.

MB324CT00TBSN60

60B21114

refresh clock divided by 60, periodic timer

enabled, type 3 address multiplexing scheme, 1 cycle

disable timer, GPL4 disabled for data sampling edge

ﬂexibility, 1 loop read, 1 loop write, 4 beats refresh

burst.

MB328CT00TBSN60

30B21114

refresh clock divided by 30, periodic timer

enabled, type 3 address multiplexing scheme, 1 cycle

disable timer, GPL4 disabled for data sampling edge

ﬂexibility, 1 loop read, 1 loop write, 4 beats refresh

burst.

MBMR

MB811171622A-100

42802114b

refresh clock divided by 42, periodic timer enabled,

type 0 address multiplexing scheme, 1 cycle

disable timer, GPL4 enabled, 1 loop read, 1 loop write,

4 beats refresh burst.

TABLE 3-6. Memory Controller Initializations For 20Mhz

Device Type

Init Value [hex]

Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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