MPC821 datasheet(48/242 Pages) NXP

48 / 242 page

Functional Description

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

shown in TABLE 4-9. "BCSR0 Description" on page 46.

4•11•3

BCSR1 - Board Control Register 1

The BCSR1 serves as a control register on the FADS. It is accessed at offset 4 from BCSR base

address. It may be read or written at any timeA. BCSR1 gets its defaults upon Power-On reset. Most

of BCSR1 pins are available at the daughter board connectors and on the expansion connectors

a. May be read and written as any other fields and are presented at their associated data pins during Hard-Reset.

b. Applicable for MPC’s revision A or above. Otherwise have no influence.

A. Provided that BCSR is not disabled.

TABLE 4-9. BCSR0 Description

BIT

MNEMONIC

FUNCTION

PON

DEF.

ATT

ERB

External Arbitration. When ’0’ during Hard-Reset, Arbitration is performed

internally. When ’1’ during Hard-Reset, Arbitration is performed externally.

R,W

Interrupt Preﬁx. When ’0’ during Hard-Reset, Interrupt preﬁx set to

0xFFF00000, if ’1’ Interrupt Preﬁx set to 0.

R,W

Reserved

Implementeda

R,W

BDIS

Boot Disable. When ’0’ during Hard-Reset, CS0~ region is enabled for boot.

When ’1’, CS0~ region is disabled for boot.

R,W

4 - 5

BPS(0:1)

Boot Port Size. Determines the port size for CS0~ at boot. ’00’ - 32 bit, ’01’ -

8 bit, ’10’ - 16 bit, ’11’ - reserved.

’00’

R,W

Reserved

Implementeda

R,W

7 - 8

ISB(0:1)

Initial Space Base. Value during Hard-Reset determines the initial base

address of the internal MPC memory map. When ’00’ - initial space at 0,

when ’01’ - initial space at 0x00F00000, when ’10’ - initial space at

0xFF000000, when ’11’ - initial space at 0xFFF00000.

’10’

R,W

9 - 10

DBGC(0:1)

Debug Pins Conﬁguration. Value during Hard-Reset determines the

function of the PCMCIA channel II pins. When ’00’ - these pins function as

PCMCIA channel II pins, when ’01’ - they serve as Watch-Points,’10’ -

Reserved, when ’11’ - they become show-cycle attribute pins, e.g., VFLS,

VF...

’11’

R,W

11-12

DBPC(0:1)

Debug Port Pins Conﬁguration. Value during Hard-Reset determines the

location of the debug port pins. When ’00’ - debug port pins are on the JTAG

port, when ’01’ - debug port non-existent, ’10’ - Reserved, when ’11’ debug

port is on PCMCIA channel II pins.

’00’

R,W

13 - 14

EBDF(0:1)b

External Bus Division Factor. Value during Hard Reset determines the

factor upon which the CLKOUT of the MPC external bus, is divided with

respect to its internal MPC clock. When ’00’ - CLKOUT is GCLK2 divided by

1, when ’01’, CLKOUT is GCLK2 divided by 2.

’00’

R,W

Reserved

Implementeda.

’0’

R,W

16 - 31

Reserved

Un-Implemented

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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