MPC821 datasheet(207/242 Pages) NXP

207 / 242 page

Support Information

MOTOROLA

MPC860TFADS Daughter Board Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

GND

BADDR30

I/O,X

Burst Address Line 30. Dedicated for external master support.

Used to generate Burst address during external master burst

cycles. Pulled - up but otherwise unused on the FADS.

GND

ALE_A

I, H

Address Latch Enable for PCMCIA slot A. Latches address in

external latches at the beginning of access to a PC-Card.

GND

BADDR29

I/O,X

Burst Address Line 29. Dedicated for external master support.

Used to generate Burst address during external master burst

cycles. Pulled - up but otherwise unused on the FADS.

GND

AS~

I/O, L

Asynchronous external master Address Strobe signal. When

asserted (L) by the external master, the MPC recognizes an

asynchronous cycle in progress. Pulled - up but otherwise unused

on the FADS.

GND

MODCK1

I/O

OP2/MODCK1/STS~. PCMCIA Output Port 2 or Mode Clock 1

input or Special Transfer Start output. Used at Power-On reset as

MODCK1. For MPC823 or MPC850 daughter boards conﬁgured

afterwards as a OP2 for all other daughter boards conﬁgured

afterwards as STS~.

GND

RESETA

I,H

PC-Card reset signal.

GND

BADDR28

I/O,X

Burst Address Line 28. Dedicated for external master support.

Used to generate Burst address during external master burst

cycles. Pulled - up but otherwise unused on the FADS.

GND

TEXP

X,X

MPC Timer Expired. Not used on the FADS.

GND

WAIT_B~

I/O, L

This signal is PCMCIA slot B wait signal. Pulled-up but otherwise

not used on the FADS.

GND

TABLE 5-10. PM2 Interconnect Signals

Pin No.

Signal Name

Attribute

Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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