MPC821 datasheet(204/242 Pages) NXP

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Support Information

MPC860TFADS Daughter Board Design Specification—Rev 0.1

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

138

GND

139

I, T.S.

MPC’s Address line 0. Not used on the FADS.

140

GND

TABLE 5-10. PM2 Interconnect Signals

Pin No.

Signal Name

Attribute

Description

V12

10V output from voltage doubler. Used to switch TMOS gates on

both mother and daughter boards. Should not be used for any

other purpose.

N.C.

DSDI

I/O

DSDI/TDI. Debug Port Serial Data Input or JTAG port serial

Data Input. Used on the FADS as debug port serial data, driven

by the debug-port controller. If the ADI bundle is not connected to

the FADS, may be driven by external debug / JTAGa port

controller.

GND

DSCK

I/O

DSCK/TCK. Debug Port Serial Clock input or JTAG port serial

clock input. Used on the FADS as debug port serial clock, driven

by the debug-port controller. If the ADI bundle is not connected to

the FADS, may be driven by an external debug / JTAGa port

controller.

DSDO

DSDO/TDO. Debug Port Serial Data Output or JTAG port Data

Output. Used on the FADS as debug port serial data. If the ADI

bundle is not connected to the FADS, may be used by an external

debug / JTAGa port controllers.

GND

AT2

I/O

IP_B2/IOIS16~/AT2. PCMCIA slot B Input Port 2 or PCMCIA 16

bit I/O capability indication or Address Type 2. For MPC823 or

MPC850 daughter boards - conﬁgured as IP_B2/IOIS16~. For all

other daughter boards, conﬁgured as AT2, but may be conﬁgured

to alternate function as no use is done with AT2 on the FADS.

GND

TABLE 5-9. PM1 Interconnect Signals

Pin No.

Signal Name

Attribute

Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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