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MPC821 bảng dữ liệu(PDF) 201 Page - NXP Semiconductors

tên linh kiện MPC821
Giải thích chi tiết về linh kiện  Design Specification
PDF  242 Pages
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Support Information
MOTOROLA
MPC860TFADS Daughter Board Design Specification—Rev 0.1
25
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
51
GPL2~
I, L
General Purpose Line 2 for UPMA or UPMB. Used with the
SDRAM, as a CAS~ signal.
52
GND
53
WE3~
I, L
GPCM Write Enable 3 or PCMCIA WE~. Selects the LSB within a
word for the Flash Simm or qualifies Writes for the PC-Card.
54
GND
55
WE2~
I, L
GPCM Write Enable 2 or PCMCIA OE~. Selects the offset 2 Byte
within a word for the Flash Simm or open data buffers for read
from PC-Card.
56
GND
57
WE1~
I, L
GPCM Write Enable1 or PCMCIA I/O Write. Used to qualify write
cycles to the Flash memory and as I/O Write for the PCMCIA
channel.
58
GND
59
BS2A~
I, L
Byte Select 2 for UPMA. Selects offset 2 bytes within Word. Used
for Dram access.
60
GND
61
WE0~
I, L
GPCM Write Enable 0 or PCMCIA I/O Read. Used to qualify write
cycles to the Flash memory and as I/O Reads from PC-Card.
62
GND
63
SPARE1
I,O, L
MPC spare line 1. Pulled - up but otherwise unused on the FADS.
64
GND
65
EDOOE~
I,L
In fact UPMA or UPMB General Purpose Line 1. Used for Output
Enable with EDO Dram simms, which have this input (most of
them don’t). Used also as RAS signal for the SDRAM.
66
GND
67
BS0A~
I, L
Byte Select 0 from UPMA. Selects offset 0 Bytes within a word.
Used as one of the CAS~ lines for Dram access.
68
GND
69
BS3A~
I, L
Byte Select 3 from UPMA. Selects offset 3 Bytes within a word.
Used as one of the CAS~ lines for Dram access.
70
GND
71
A31
I, T.S.
MPC’s Address line 31.
72
GND
73
BS1A~
I, L
Byte Select 1 from UPMA. Selects offset 1 Bytes within a word.
Used as one of the CAS~ lines for Dram access.
74
GND
TABLE 5-9. PM1 Interconnect Signals
Pin No.
Signal Name
Attribute
Description
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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