MPC821 datasheet(208/242 Pages) NXP

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Support Information

MPC860TFADS Daughter Board Design Specification—Rev 0.1

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MODCK2

I/O

OP3/MODCK2/DSDO. PCMCIA Output Port 3 or Mode Clock 2

input or Special Transfer Start output. Used at Power-On reset as

MODCK2 and conﬁgured afterwards as a OP3. May be used

with alternate function.

GND

N.C.

GND

SRESET~

I/O, L,

O.D.

MPC Soft Reset. Driven by on-board logic and may be driven by

off-board logic with Open-Drain gate only.

GND

PORST~

X, L

Power On reset for the MPC. Not used on the FADS, generated

on the daughter boards

GND

HRESET~

I/O, L,

O.D.

MPC Hard Reset. Driven by on-board logic and may be driven by

off-board logic with Open-Drain gate only.

GND

RSTCNF~

O, L

Hard Reset Conﬁguration output. Driven during Hard Reset to the

daughter board to signal the MPC that it should sample Hard

Reset conﬁguration from the data bus.

GND

R_PORI~

O, L

Main battery power-on reset. Generated as a result of main 3.3V

bus going through power up or power-down. Drives on-board

logic as well either HARD-RESET or Power-On reset to the MPC.

GND

BWAITA~

O, L

Buffered PCMCIA slot A WAIT signal. Used to prolong cycles to

slow PC-Cards. In case of MPC823 or MPC850 daughter boards,

connected to WAIT_B~ signal of the MPC.

GND

BWP

O, H

Buffered PCMCIA slot A Write Protect. In fact IP_A2/IOIS16A~.

Used as PC-card write protect indication or as 16 bit I/O capability

indication for PCMCIA slot A. In case of MPC823 or MPC850

daughter boards, connected to IP_B2 signal of the MPC.

TABLE 5-10. PM2 Interconnect Signals

Pin No.

Signal Name

Attribute

Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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