S32K310 datasheet(113/137 Pages) NXP

113 / 137 page

Figure 54. QuadSPI output timing (SDR mode)

12.6.2 QuadSPI Octal 3.3V DDR 100MHz

The following table describes the QuadSPI electrical characteristics. Measurements are with maximum output load of 25pF, input

transition of 1ns and pads configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97V to 3.63V. QuadSPI

trace length should be less than or equal to 2 inches. For Single and Dual IO modes of operation if external device doesn’t have

pull-up feature, then external pull-up must be added at board level for unused device pins. With external pull-up, performance

of the interface may degrade in Quad IO mode based on load associated with external pull-up. QuadSPI support delay chain

upto length 16, wherein delay length of low-frequency segment is 16 and length of high-frequency segment is 0. See the device

Reference Manual for register and bit descriptions.

Set FLSHCR[TCSS]=2 and FLSHCR[TCSH]=5.

Table 51. QuadSPI Octal 3.3V DDR 100MHz

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

fSCK_DQS

SCK / DQS

frequency 1

—

100

MHz

—

tSDC

SCK duty cycle

—

tCL_SCK_DQS

SCK / DQS low

time 1

4.500

—

tCH_SCK_DQS

SCK / DQS high

time 1

4.500

—

tOD_DATA

Data output delay

(w.r.t. SCK)

1.016

—

3.484

—

tOD_CS

CS output delay

(w.r.t. SCK) 2

3.016 - n/

fSCK

—

-0.016 +

m/fSCK

—

tDVW

Input data valid

window 1

3.284

—

tISU_DQS

Input setup time

(w.r.t. DQS) 1

-0.816

—

tIH_DQS

Input hold time (w.r.t.

DQS) 1

3.684

—

NXP Semiconductors

Communication interfaces

S32K3xx Data Sheet, Rev. 5.2, 10/2022

Data Sheet: Technical Data

Preliminary Information

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