S32K310 datasheet(111/137 Pages) NXP

111 / 137 page

MDC (output)

MDIO (output)

MDIO (input)

MDC6

MDC5

MDC3

MDC4

MDC1

MDC2

Figure 52. MII/RMII serial management channel timing

12.6 QuadSPI

12.6.1 QuadSPI Quad 3.3V SDR 120MHz

The following table describes the QuadSPI electrical characteristics. Measurements are with maximum output load of 25pF, input

transition of 1ns and pads configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97V to 3.63V. QuadSPI

trace length should be less than or equal to 2 inches. For Single and Dual IO modes of operation if external device doesn’t have

pull-up feature, then external pull-up must be added at board level for unused device pins. With external pull-up, performance

of the interface may degrade in Quad IO mode based on load associated with external pull-up. QuadSPI support delay chain

upto length 16, wherein delay length of low-frequency segment is 16 and length of high-frequency segment is 0. See the device

Reference Manual for register and bit descriptions.

Program register value QuadSPI_FLSHCR[TCSS] = 4`h3.

Program register value QuadSPI_FLSHCR[TCSH] = 4`h3.

Program register value QuadSPI_DLLCRA[SLV_FINE_OFFSET] to 4'b0001.

Table 50. QuadSPI Quad 3.3V SDR 120MHz

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

fSCK

SCK clock

frequency 1

—

120

MHz

Pad Loopback

—

fSCK

SCK clock

frequency 1

—

MHz

Internal Loopback

—

tSCK

SCK clock period

1/fSCK

—

Pad Loopback

—

tSCK

SCK clock period

1/fSCK

—

Internal Loopback

—

tSDC

SCK duty cycle 2

—

Internal Loopback

—

tSDC

SCK duty cycle 2

—

Pad Loopback

—

tIS

Data input setup

time

1.75

—

Pad Loopback

—

tIS

Data input setup

time

—

Internal Loopback

—

Table continues on the next page...

NXP Semiconductors

Communication interfaces

S32K3xx Data Sheet, Rev. 5.2, 10/2022

Data Sheet: Technical Data

Preliminary Information

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