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S32K310 bảng dữ liệu(PDF) 98 Page - NXP Semiconductors

tên linh kiện S32K310
Giải thích chi tiết về linh kiện  Supports S32K344, S32K324, S32K314, S32K312, S32K341 and S32K342. Data is preliminary for S32K311, S32K310, S32K328, S32K338, S32K348, S32K358 and S32K388
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Trang chủ  http://www.nxp.com
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S32K310 bảng dữ liệu(HTML) 98 Page - NXP Semiconductors

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2. For LPSPI0 instance, max. peripheral frequency is equal to AIPS_PLAT_CLK.
3. fperiph = LPSPI peripheral clock
4. Master Loopback mode: In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting
LPSPI_CFGR1[SAMPLE] bit as 1.
5. These specifications apply to the SPI operation, as master or slave, at up to 10 Mbps for the combinations not indicated
in the table below. Unless otherwise noted, all other ‘master’ and ‘slave’ specifications are also applicable in the 10Mbps
configurations. See table "LPSPI 20 MHz and 15 MHz Combinations.
6. LPSPI0 support up to 20MHz on fast pin.
7. Minimum configuration value for CR[PCSSCK] field is 3(0x00000011).
8. Minimum configuration value for CCR[SCKPCS] field is 3(0x00000011).
9. While selecting odd dividers, ensure Duty Cycle is meeting this parameter.
fperiph = LPSPI peripheral clock
MSB OUT2
LSB OUT
BIT 6 ... 1
MSB IN2
SS1
(OUTPUT)
SPSCK
(CPOL = 0)
(OUTPUT)
SPSCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
LSB IN
BIT 6 ... 1
3
5
5
7
10
11
6
12
13
12
13
4
2
Figure 38. LPSPI Master Mode Timing (CPHA=0)
PORT DATA
PORT DATA
MASTER MSB OUT
MASTER LSB OUT
BIT 6 ... 1
MSB IN2
SS1
(OUTPUT)
SPSCK
(CPOL = 0)
(OUTPUT)
SPSCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
LSB IN
BIT 6 ... 1
3
5
5
7
10
11
6
12
13
12
13
4
2
Figure 39. LPSPI Master Mode Timing (CPHA=1)
NXP Semiconductors
Communication interfaces
S32K3xx Data Sheet, Rev. 5.2, 10/2022
Data Sheet: Technical Data
Preliminary Information
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