S32K310 datasheet(5/137 Pages) NXP

5 / 137 page

1 Overview

The S32K3xx product series further extends the highly-scalable portfolio of Arm ® Cortex ® - M0+/M4F S32K1xx chips in the

automotive industry with the Arm Cortex-M7 core at higher frequency, more memory, ASIL-B and D rating and advanced security

module. With a focus on automotive environment robustness, the S32K3xx product series devices are well suited to a wide range

of applications in electrical harsh environments, and are optimized for cost-sensitive applications offering new, space saving

package options. The S32K3xx series offers a broad range of memory, peripherals and performance options. Devices in this

series share common peripherals and pin-out, allowing developers to migrate easily within a chip series or among other chip series

to take advantage of more memory or feature integration.

S32K3x1, and S32K3x8 specific information is preliminary until these devices are qualified and may change

without notice.

CAUTION

2 Block diagram

The following figures show the S32K3xx product series block diagrams

Fabric

Memory

512 KB Pflash with ECC

64 KB Dflash with ECC

112 KB RAM with ECC

include 96 KB TCM

System

Debug/Trace (SWD/JTAG/ETB)

FXOSC (8-40MHz)

32ch ext. INT/WKUP

Security: HSE-B

Symmetric Hardware Accelerators

Lifecycle

Management

XRDC

Access control

FIRC (48MHz)

SIRC (32KHz)

PLL

12ch DMA

Analog/Timers

2 x 24ch 12bit ADC

1 x LPCMP

2x24ch 16bit eMIOS Timer

BCTU (Body Control Trigger Unit)

LCU (Logic Control Unit)

MPU

CRC

FCCU

EIM/ERM

SWT

Functional Safety

CMU

STCU

Communication

4 x LPSPI

2 x LPI2C

Network

3 x FlexCAN,

all ch support CAN FD

CPU Platform

Xbar (64bit)

Cortex-M0+

RAM

Single

Core

Cortex-M7

FPU, DSP

120Mhz

I-Cache

D-cache

16ch FlexIO

Emulating

UART, I2C, SPI,

I2S, SENT, PWM

4 x LPUART (LIN)

Asymmetric Hardware Accelerators

32bit RTC

TRNG/PRNG

Memory

•

OTA ready -

RWW, A/B swap

CPU Platform

•

Scalable ARM M7

core in lockstep

•

Optimized for Real-

time with zero wait

I/D-TCM

Network/

Communication

•

CAN/ CAN FD, LIN

•

Flexible IO emulation

Motor Control

•

On-chip motor

control sub-

system

•

Offloading CPU

• Future Proof Security/OTA

• ISO26262 Compliant Safety System

• Scalable ARM platform

• Optimized for Low power

• Rich Network/Communication Interface

Safety

•

HW redundancy

•

MBIST/LBIST/Self Test

•

Clock/Voltage monitor

•

Centralized error

detection

•

ASIL B compliant

Security

•

HW accl for AES 256,

RSA 4096, ECC 521

•

Firmware included,

upgradable

•

Side-channel physical

protection

•

Meet Evita Full

function goal

Figure 1. S32K310: ASIL B Single Core 1MB General Purpose MCU

NXP Semiconductors

Overview

S32K3xx Data Sheet, Rev. 5.2, 10/2022

Data Sheet: Technical Data

Preliminary Information

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