S32K310 datasheet(80/137 Pages) NXP

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2. Typical program and erase times represent the median performance and assume nominal supply values and operation at

25 °C. Typical program and erase times may be used for throughput calculations.

3. Conditions: ≤ 25 cycles, nominal voltage.

4. Plant Programing times provide guidance for timeout limits used in the factory.

5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.

Typical End of Life program and erase values may be used for throughput calculations.

6. Conditions: -40°C ≤TJ ≤150°C, full spec voltage.

9.2 Flash memory Array Integrity and Margin Read specifications

Table 27. Flash memory Array Integrity and Margin Read specifications

Symbol

Characteristic

Min

Typical

Max1 2

Units3

tai256kseq

Array Integrity time and Margin

Read time for sequential sequence

on 256KB block.

—

8192 x Tperiod x Nread

(plus 40uS adder required if User

Margin Read)

—

tai512kseq

Array Integrity time and Margin

Read time for sequential sequence

on 512KB block.

—

16384 x Tperiod x Nread

(plus 40uS adder required if User

Margin Read)

—

tai1mseq

Array Integrity time and Margin

Read time for sequential sequence

on 1MB block.

—

32768 x Tperiod x Nread

(plus 40uS adder required if User

Margin Read)

—

tai2mseq

Array Integrity time and Margin

Read time for sequential sequence

on 2MB block.

—

65536 x Tperiod x Nread

(plus 40uS adder required if User

Margin Read)

—

tai256kprop

Array Integrity time for proprietary

sequence on 256KB block.

—

106496

x Tperiod x Nread

—

tai512kprop

Array Integrity time for proprietary

sequence on 512KB block.

—

229376

x Tperiod x Nread

—

tai1mprop

Array Integrity time for proprietary

sequence on 1MB block.

—

491520

x Tperiod x Nread

—

tai2mprop

Array Integrity time for proprietary

sequence on 2MB block.

—

1048576

x Tperiod x Nread

—

1. Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The

equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and

Nread (which is the number of clocks required for read, including single read, dual read, quad read contribution. Thus for a

read setup that requires 6 clocks to read Nread would equal 6.

2. Array Integrity times are actual hardware execution times and do not include software overhead or system code execution

overhead.

3. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the

equation, the results of the equation are also unit accurate.

NXP Semiconductors

Flash memory specification

S32K3xx Data Sheet, Rev. 5.2, 10/2022

Data Sheet: Technical Data

Preliminary Information

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