S32K310 datasheet(92/137 Pages) NXP

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Table 38. PLL (continued)

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

FPLL_vcoRange

VCO Frequency

range

640

—

1280

MHz

—

FPLL_DS

Modulation Depth

(down spread)

-0.5

—

-3

—

FPLL_FM

Modulation

frequency

—

KHz

—

TPLL_start

PLL lock time

—

JPLL_cyc

PLL period jitter (pk-

pk) 1, 2, 3

—

237

FPLL_out = 240MHz,

Integer Mode

—

JPLL_cyc

PLL period jitter (pk-

pk) 1, 2, 3

—

487

FPLL_out = 240MHz,

Fractional Mode

—

JPLL_acc

PLL accumulated

jitter (pk-pk) 1, 2, 3

—

840

FPLL_out = 240MHz,

Integer Mode

—

JPLL_acc

PLL accumulated

jitter (pk-pk) 1, 2, 3

—

1680

FPLL_out = 240MHz,

Fractional Mode

—

JPLL_cyc

PLL period jitter (pk-

pk) 1, 2, 3

—

295

FPLL_out = 160MHz,

Integer Mode

—

JPLL_cyc

PLL period jitter (pk-

pk) 1, 2, 3

—

670

FPLL_out = 160MHz,

Fractional Mode

—

JPLL_acc

PLL accumulated

jitter (pk-pk) 1, 2, 3

—

840

FPLL_out = 160MHz,

Integer Mode

—

JPLL_acc

PLL accumulated

jitter (pk-pk) 1, 2, 3

—

1680

FPLL_out = 160MHz,

Fractional Mode

—

JPLL_cyc

PLL period jitter (pk-

pk) 1, 2, 3

—

353

FPLL_out = 120MHz,

Integer Mode

—

JPLL_cyc

PLL period jitter (pk-

pk) 1, 2, 3

—

853

FPLL_out = 120MHz,

Fractional Mode

—

JPLL_acc

PLL accumulated

jitter (pk-pk) 1, 2, 3

—

840

FPLL_out = 120MHz,

Integer Mode

—

JPLL_acc

PLL accumulated

jitter (pk-pk) 1, 2, 3

—

1680

FPLL_out = 120MHz,

Fractional Mode

—

1. For SSCG, jitter due to systematic modulation needs to be added as per applied modulation.

2. Jitter numbers are valid only at IP boundary and does not include any degradation due to IO pad for clock measurement.

3. Jitter numbers calculated by extrapolating RMS jitter numbers to +/- 7 sigma .

NXP Semiconductors

Clocking modules

S32K3xx Data Sheet, Rev. 5.2, 10/2022

Data Sheet: Technical Data

Preliminary Information

92 / 137

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