S32K310 datasheet(83/137 Pages) NXP

83 / 137 page

Table 30. Flash Read Wait State Settings (S32K344, S32K324, S32K314, S32K342, S32K322, S32K341, S32K312,

S32K311 and S32K310) (continued)

Flash Frequency

RWSC setting

200 MHz < Freq ≤ 233 MHz

233 MHz < Freq ≤ 250 MHz

Table 31. Flash Read Wait State Settings (S32K358, S32K348, S32K338, S32K328 and S32K388)

Flash Frequency

RWSC setting

250 KHz < Freq ≤ 60 MHz

60 MHz < Freq ≤ 90 MHz

90 MHz < Freq ≤ 120 MHz

120 MHz < Freq ≤ 150 MHz

150 MHz < Freq ≤ 180 MHz

180 MHz < Freq ≤ 210 MHz

210 MHz < Freq ≤ 240 MHz

240 MHz < Freq ≤ 250 MHz

10 Analog modules

10.1 SAR ADC

All below specs are applicable when only one ADC instance is in operation and averaging is used. GPIO activity on pins adjacent

to ADC channels, or reference, may introduce some degradation on the analog input paths. For parallel/simultaneous operation

of two or three ADCs, either for sampling the same channel by each ADC, or for sampling different channels by each ADC,

some amount of decrease in performance can be expected. Care must be taken to stagger each ADC conversions, in particular

the sample phase, to minimize the impact of simultaneous conversions. ADC performance specifications are guaranteed when

calibration uses maximum averaging i.e. when AVGEN = 1 and AVGS = 3. When using ADC averaging, see Reference Manual

to determine the most appropriate settings for AVGS.

Table 32. SAR ADC

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

VDD_HV_A

ADC Supply

Voltage 1

2.97

—

5.5

—

DVREFL

VSS / VREFL

Voltage Difference 2

-100

—

100

—

VAD_INPUT

ADC Input Voltage 3 VREFL

—

VREFH

—

Table continues on the next page...

NXP Semiconductors

Analog modules

S32K3xx Data Sheet, Rev. 5.2, 10/2022

Data Sheet: Technical Data

Preliminary Information

83 / 137

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