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S32K310 bảng dữ liệu(PDF) 112 Page - NXP Semiconductors

tên linh kiện S32K310
Giải thích chi tiết về linh kiện  Supports S32K344, S32K324, S32K314, S32K312, S32K341 and S32K342. Data is preliminary for S32K311, S32K310, S32K328, S32K338, S32K348, S32K358 and S32K388
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Table 50. QuadSPI Quad 3.3V SDR 120MHz (continued)
Symbol
Description
Min
Typ
Max
Unit
Condition
Spec
Number
tIH
Data input hold time 1
—
—
ns
Pad Loopback
—
tIH
Data input hold time 1
—
—
ns
Internal Loopback
—
tOV
Data output valid
time
—
—
1.75
ns
Pad Loopback
—
tOV
Data output valid
time
—
—
1.75
ns
Internal Loopback
—
tIV
Data output invalid
time
-1.5
—
—
ns
Pad Loopback
—
tIV
Data output invalid
time
-1.5
—
—
ns
Internal Loopback
—
tCSSCK
CS to SCK time
5
—
—
ns
Pad Loopback
—
tCSSCK
CS to SCK time
5
—
—
ns
Internal Loopback
—
tSCKCS
SCK to CS time
3
—
—
ns
Pad Loopback
—
tSCKCS
SCK to CS time
3
—
—
ns
Internal Loopback
—
1. This frequency specification is valid only if output valid time of external flash is ≤ 5.5ns, and if output valid time of
external flash is more than 5.5ns but ≤ 6.5ns, then maximum fSCK is 104MHz.
2. For S32K342 100MQFP, tSDC spec would be 44%-56% when ENET and SAI active along with QuadSPI at 120MHZ
Figure 53. QuadSPI input timing (SDR mode)
NXP Semiconductors
Communication interfaces
S32K3xx Data Sheet, Rev. 5.2, 10/2022
Data Sheet: Technical Data
Preliminary Information
112 / 137



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