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S32K310 bảng dữ liệu(PDF) 116 Page - NXP Semiconductors |
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S32K310 bảng dữ liệu(HTML) 116 Page - NXP Semiconductors |
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116 / 137 page  SD4 SD5 SDx_CLK Output from uSDHC to card SDx_DATA[7:0] Input from card to uSDHC SDx_DATA[7:0] SD3 SD2 SD6 SD7 SD8 SD1 Figure 55. SD/eMMC4.3 High Speed Mode Interface Timing 12.7.2 uSDHC DDR electrical specifications The following table describes the uSDHC electrical characteristics. Measurements are with maximum output load of 25pF, input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V. Table 54. uSDHC DDR electrical specifications Symbol Description Min Typ Max Unit Condition Spec Number fpp Clock frequency (eMMC4.4/4.41 DDR) 1 — — 50 MHz Medium pad SD1 fpp Clock frequency (eMMC4.4/4.41 DDR) 1 — — 25 MHz Standard pad SD1 fpp Clock frequency (SD3.0 DDR) 1 — — 50 MHz Medium pad SD1 fpp Clock frequency (SD3.0 DDR) 1 — — 25 MHz Standard pad SD1 tWL Clock low time 6 — — ns Medium pad — tWL Clock low time 12 — — ns Standard pad — tWH Clock high time 6 — — ns Medium pad — tWH Clock high time 12 — — ns Standard pad — tTLH Clock rise time 1, 2 — — 4 ns Medium pad — tTLH Clock rise time 1, 2 — — 8 ns Standard pad — tTHL Clock fall time 1, 2 — — 4 ns Medium pad — tTHL Clock fall time 1, 2 — — 8 ns Standard pad — tOD SDHC output delay (output valid) 1 2.7 — 5.6 ns SDHC_CLK to SDHC_ DAT SD2 Table continues on the next page... NXP Semiconductors Communication interfaces S32K3xx Data Sheet, Rev. 5.2, 10/2022 Data Sheet: Technical Data Preliminary Information 116 / 137 |
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