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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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S32K310 bảng dữ liệu(PDF) 115 Page - NXP Semiconductors |
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S32K310 bảng dữ liệu(HTML) 115 Page - NXP Semiconductors |
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115 / 137 page  12.7 uSDHC 12.7.1 uSDHC SDR electrical specifications The following table describes the uSDHC electrical characteristics. Measurements are with maximum output load of 25pF, input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V. Table 53. uSDHC SDR electrical specifications Symbol Description Min Typ Max Unit Condition Spec Number fpp Clock frequency (low speed) 1, 2 — — 400 kHz — SD1 fpp Clock frequency 2, 3 — — 50 MHz Medium pad SD1 fpp Clock frequency 2, 4 — — 25 MHz Standard pad SD1 fOD Clock frequency (identification mode) 2 100 — 400 kHz — SD1 tWL Clock low time 6 — — ns Medium pad SD2 tWL Clock low time 12 — — ns Standard pad SD2 tWH Clock high time 6 — — ns Medium pad SD3 tWH Clock high time 12 — — ns Standard pad SD3 tTLH Clock rise time 2, 5 — — 4 ns Medium pad SD4 tTLH Clock rise time 2, 5 — — 8 ns Standard pad SD4 tTHL Clock fall time 2, 5 — — 4 ns Medium pad SD5 tTHL Clock fall time 2, 5 — — 8 ns Standard pad SD5 tOD SDHC output delay (output valid) 2 -5.6 — 2.6 ns SDHC_CLK to SDHC_ CMD / SDHC_DAT SD6 tISU SDHC Input setup time 6 6.3 — — ns fpp=25 MHz, 400 KHz, SDHC_CMD / SDHC_ DAT to SDHC_CLK, SD7 tISU SDHC Input setup time 6 4.8 — — ns fpp=50 MHz, SDHC_ CMD / SDHC_DAT to SDHC_CLK, SD7 tIH SDHC Input hold time 6 1.5 — — ns SDHC_CLK to SDHC_ CMD / SDHC_DAT SD8 1. In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7V to 3.6V. 2. Output timing valid for maximum external load CL = 25pF, which is assumed to be a 10pF load at the end of a 50Ohm, un-terminated, 3.5 inch microstrip trace on standard FR4 (1.5pF/inch), (25pF total with margin). 3. In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode, clock frequency can be any value between 0–50 MHz. 4. In normal (full) speed mode for MMC card, clock frequency can be any value between 0–25 MHz. In high-speed mode, clock frequency can be any value between 0–50 MHz. 5. The SDHC_CLK rise/fall time specification applies to the input clock transition required in order to meet the output delay specifications. SDHC_CLK output transition time is dependent on output load and GPIO pad drive strength. See the GPIO pad specifications for detail. 6. Input timing assumes an input signal slew rate of 3ns (20%/80%). NXP Semiconductors Communication interfaces S32K3xx Data Sheet, Rev. 5.2, 10/2022 Data Sheet: Technical Data Preliminary Information 115 / 137 |
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