CS48L32 datasheet(5/192 Pages) CIRRUS

5 / 192 page

Cirrus Logic

DS1219F4

CS48L32

1.3 Pin Descriptions

IN1RN_1/IN2_

PDMCLK

VOUT_MIC or

MICBIAS1 [1]

I/O

Right-channel negative differential mic/line

input/IN2 PDM clock.

IN1RN_1 input

IN1RN_2

VOUT_MIC

Right-channel negative differential mic/line

input.

—

Input

IN1RP_1/IN2_

PDMDATA

VOUT_MIC or

MICBIAS1 [1]

Right-channel single-ended mic/line input/

positive differential mic/line input/IN2 PDM data

input.

PD/H

IN1RP_1 input

IN1RP_2

VOUT_MIC

Right-channel single-ended mic/line input/

positive differential mic/line input.

—

Input

MICBIAS1A

VOUT_MIC

Microphone bias 1A

—

Output

MICBIAS1B

VOUT_MIC

Microphone bias 1B

—

Output

MICBIAS1C

VOUT_MIC

Microphone bias 1C

—

Output

VOUT_MIC

—

LDO2 output decoupling pin (generated

internally by CS48L32). Can also be used as

reference/supply for external microphones.

—

Output

VREF_FILT

—

Band-gap reference external capacitor

connection

—

Output

Digital I/O

ASP1_BCLK/

GPIO5

VDD_IO

I/O

Audio serial port 1 bit clock/GPIO5

PU/PD/K/H/

Z/C/OD

GPIO5 input

with bus-keeper

ASP1_DIN/

GPIO4

VDD_IO

Audio serial port 1 data input/GPIO4

PU/PD/K/H/

C/OD

GPIO4 input

with bus-keeper

ASP1_DOUT/

GPIO3

VDD_IO

Audio serial port 1 data output/GPIO3

PU/PD/K/H/

Z/C/OD

GPIO3 input

with bus-keeper

ASP1_

FSYNC/

GPIO6

VDD_IO

I/O

Audio serial port 1 frame sync/GPIO6

PU/PD/K/H/

Z/C/OD

GPIO6 input

with bus-keeper

ASP2_BCLK/

GPIO9

VDD_IO

I/O

Audio serial port 2 bit clock/GPIO9

PU/PD/K/H/

Z/C/OD

GPIO9 input

with bus-keeper

ASP2_DIN/

GPIO8

VDD_IO

I/O

Audio serial port 2 data input/GPIO8

PU/PD/K/H/

C/OD

GPIO8 input

with bus-keeper

ASP2_DOUT/

GPIO7

VDD_IO

I/O

Audio serial port 2 data output/GPIO7

PU/PD/K/H/

Z/C/OD

GPIO7 input

with bus-keeper

ASP2_

FSYNC/

GPIO10

VDD_IO

I/O

Audio serial port 2 frame sync/GPIO10

PU/PD/K/H/

Z/C/OD

GPIO10 input

with bus-keeper

AUXPDM1_

CLK

VDD_IO

I/O

Auxiliary PDM 1 clock

PD/H/C

Input

AUXPDM1_

DOUT

VDD_IO

Auxiliary PDM 1 data output

Output

AUXPDM2_

CLK

VDD_IO

I/O

Auxiliary PDM 2 clock

PD/H/C

Input

AUXPDM2_

DOUT

VDD_IO

Auxiliary PDM 2 data output

Output

GPIO1

VDD_IO

I/O

GPIO1

PU/PD/K/H/

C/OD

GPIO1 input

with bus-keeper

GPIO2

VDD_IO

I/O

GPIO2

PU/PD/K/H/

C/OD

GPIO2 input

with bus-keeper

IRQ

VDD_IO

Interrupt request (IRQ) output (default is active

low)

C/OD

Open-drain

output

MCLK1

VDD_IO

Master clock 1

PD/H

Input

RESET

VDD_IO

Digital reset input (active low)

PU/PD/K/H

Input with

pull-up

Table 1-1. Pin Descriptions (Cont.)

PU = Pull-up, PD = Pull-down, K = Bus keeper, H = Hysteresis on CMOS input, Z = Hi-Z (High impedance), C = CMOS, OD = Open drain.

Pin Name

Pin #

(WLCSP)

Pin #

(QFN)

Power

Supply

I/O

Pin Description

Digital Pad

Attributes

State at Reset

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