AD9083BBCZ datasheet(85/93 Pages) AD

85 / 93 page

Data Sheet

AD9083

Rev. 0 | Page 85 of 93

Addr.

Name

Bits

Bit Name

Description

Reset Access

0x521 CBUS_WDATA

[7:0]

CBUS_WDATA_JTX_PLL_RC

Control Bus data,. Control Bus data, channel

selected with cbus_wstrobe_ser signal

0x0

R/W

0x522 CBUS_RDATA

[7:0]

CBUS_RDATA_JTX_PLL_RS

Read back bus, channel selected bwith

cbus_ren_ser.

0x0

0x523 REFCLK_CTRL

RESERVED

Reserved.

0x0

[6:3]

SEL_REFCLK_RCVR_CM_CTRL Synca for refclk.

0x0

R/W

SEL_REFCLK_RCVR_LP_MODE

_RC

Synca for refclk.

0x0

R/W

SEL_SYNCA_FOR_REFCLK_RC Synca for refclk.

0x0

R/W

EN_REFCLK_RCVR_RC

Synca for refclk.

0x1

R/W

0x524 JTX_PLL_REV_ID_RS

[7:0]

JTX_PLL_REV_ID_RS

Read back bus, channel selected bwith

cbus_ren_ser.

0x0

0xB90 POWER_DOWN_REG

EN_CAL_ANA

Enable Calibration Analog Blocks, Set to 0 for

Power-down.

0x0

R/W

EN_CAL_CLK

Enable Calibration Clock and Digital Blocks, Set

to 0 for Power-down.

0x0

R/W

EN_34

Enable Additional Two Signal Channels for 3dB

Noise Improvement.

0x0

R/W

[4:3]

PIN_PD_MODE

Power down mode.

0x0

R/W

00: power down pin disabled.

01: power down pin disables clock path only.

10: power down pin disables adc clock and vti

bias.

11: power down pin disables adc clock, vti bias

and adc masterbias block.

EN_BIAS

Enable for Adc Bias Block, Set to 0 for Power-

down.

0x0

R/W

EN_ADCCLK

Enable Channel I Adc Clock, Set to 0 for Power-

down.

0x0

R/W

EN_VTI

Enable Channel I Analog Front End, Set to 0 for

Power-down.

0x0

R/W

0xB91 ENABLE_CH7_0_REG

EN_ADC7

Enable for Channel 7 Adc Clock.

0x0

R/W

EN_ADC6

Enable for Channel 6 Adc Clock.

0x0

R/W

EN_ADC5

Enable for Channel 5 Adc Clock.

0x0

R/W

EN_ADC4

Enable for Channel 4 Adc Clock.

0x0

R/W

EN_ADC3

Enable for Channel 3 Adc Clock.

0x0

R/W

EN_ADC2

Enable for Channel 2 Adc Clock.

0x0

R/W

EN_ADC1

Enable for Channel 1 Adc Clock.

0x0

R/W

EN_ADC0

Enable for Channel 0 Adc Clock.

0x0

R/W

0xB92 ENABLE_CH15_8_REG

EN_ADC15

Enable for Channel 15 Adc Clock.

0x0

R/W

EN_ADC14

Enable for Channel 14 Adc Clock.

0x0

R/W

EN_ADC13

Enable for Channel 13 Adc Clock.

0x0

R/W

EN_ADC12

Enable for Channel 12 Adc Clock.

0x0

R/W

EN_ADC11

Enable for Channel 11 Adc Clock.

0x0

R/W

EN_ADC10

Enable for Channel 10 Adc Clock.

0x0

R/W

EN_ADC9

Enable for Channel 9 Adc Clock.

0x0

R/W

EN_ADC8

Enable for Channel 8 Adc Clock.

0x0

R/W

0xB94 VTI_GAIN_REG

[7:6]

RESERVED

Reserved

0x0

[5:0]

BGAIN

Bgain Adjustment.

0x0

R/W

0xB95 VTI_LPF_CAP_REG

[7:6]

RESERVED

Reserved

0x0

[5:0]

BCAP

Bcap Adjustment.

0x0

R/W

0xB99 DITHER_DAC_

CURRENT1_REG

[7:0]

BDITHDAC1

Bdither DAC1.

0x0

R/W

0xB9A DITHER_DAC_

CURRENT2_REG

[7:0]

BDITHDAC2

Bdither DAC2.

0x0

R/W

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