AD9083BBCZ datasheet(84/93 Pages) AD

84 / 93 page

AD9083

Data Sheet

Rev. 0 | Page 84 of 93

Addr.

Name

Bits

Bit Name

Description

Reset Access

0x508 PLL_DIV2

[7:0]

B_JTX_PLL_RC

Selects PLL feedback divider. Sets integer

division rate as N=8*B, where B=5 is its minimum

value. (divb)

0x5

R/W

0x50A PLL_DIVOVD

[7:4]

RESERVED

Reserved.

0x0

RXDIVRATEOVD_JTX_PLL_RC Override rxdivrate.

0x0

R/W

REFINDIVOVD_JTX_PLL_RC

Override refindiv.

0x1

R/W

DIVMOVD_JTX_PLL_RC

Override divm control.

0x1

R/W

BOVD_JTX_PLL_RC

Bypass from octave cal (use b_JTX_PLL_rc).

0x1

R/W

0x50B PLL_RXDIVRATE

[7:4]

RESERVED

Reserved.

0x0

[3:0]

RXDIVRATE_JTX_PLL_RC

When refindivovd is 1, sets value for rx_divrate.

0x8

R/W

0x50C PLL_VCO_TRIM

[7:6]

RESERVED

Reserved.

0x0

[5:0]

VCORTRIM_JTX_PLL_RC

Trim code slaved to 6-bits in the bandgap.

0x0

R/W

0x50D PLL_REFCLK_CPL

[7:2]

RESERVED

Reserved.

0x0

SEL_REFINDIV3_JTX_PLL_RC

Enables additional /3 on input reference clock to

PLL.

0x0

R/W

SEL_REFCKDCACB_JTX_PLL_RC Determines whether the reference clock input

should be DC-coupled (1) or AC coupled (0)

0x1

R/W

0x50E CBUS_REN_JTX_PLL

[7:1]

RESERVED

Reserved.

0x0

CBUS_REN_JTX_PLL_RC

Read enable for JTX_PLL registers.

0x0

R/W

0x50F CBUS_WSTROBE_JTX_

PLL

[7:1]

RESERVED

Reserved.

0x0

CBUS_WSTROBE_JTX_PLL_RC Write Strobe for JTX_PLL registers.

0x0

R/W

0x510 CKDIST_PD

[7:2]

RESERVED

Reserved.

0x0

IDIST_PD_RC

Enable output clocks to serializer.

1 : Enable

0x0

R/W

PD_PPF_DES_RC

Enable output clocks to serializer

1 : Enable

0x0

R/W

0x511 POLYPHASE_CTRL

[7:0]

TRIM_POLYPHASE_DES_RC

DESIGNER DEBUG: Polyphase control. DESIGNER

DEBUG: Polyphase control: <6:5>:

ppf_divm_od<1:0>, <4>: en_ppf_divm_od,

<3:1>: inv_str_od<2:0>, <0>: en_inv_str_od.

0x2F

R/W

0x512 PLL_READ_FREQ4

[7:0]

VCOFREQBAND_JTX_PLL_

RS[7:0]

VCO frequency control word that sets VCO

frequency, 00: max. VCO frequency, 7FF: min.

VCO frequency

0x0

0x513 PLL_READ_FREQ5

[7:3]

RESERVED

Reserved.

0x0

[2:0]

VCOFREQBAND_JTX_PLL_RS[

10:8]

VCO frequency control word that sets VCO

frequency, 00: max. VCO frequency, 7FF: min.

VCO frequency

0x0

0x514 PLL_PTAT_STARTUP

[7:0]

PTAT_STARTUP_JTX_PLL_RC

PTAT startup control.

0x0

R/W

0x515 PLL_PTAT_STARTUP_

STATUS1

[7:1]

RESERVED

Reserved.

0x0

PTAT_STARTUP_STATUS_RS1 PTAT startup status.

0x0

0x516 PLL_PTAT_STARTUP_

STATUS2

[7:1]

RESERVED

Reserved.

0x0

PTAT_STARTUP_STATUS_RS2 PTAT startup status.

0x0

0x517 PLL_TEMP

[7:1]

RESERVED

Reserved.

0x0

TDEGCINIT_JTX_PLL_RC

Low-to-High transition activates on-chip

temperature measurement.

0x0

R/W

0x51E PLL_LOCK_CTL1

[7:4]

JTX_PLL_LOCK_DIVIDER[3:0]

PLL Lock counter.

0x0

R/W

[3:1]

RESERVED

Reserved.

0x0

JTX_PLL_LOCK_SEL

PLL lock and timer based lock select. Select

between PLL lock signal and timer based lock

signal generation

0x0

R/W

0x51F PLL_LOCK_CTL2

[7:6]

RESERVED

Reserved.

0x0

[5:0]

JTX_PLL_LOCK_DIVIDER[9:4]

PLL Lock counter.

0x0

R/W

0x520 CBUS_ADDR

[7:0]

CBUS_ADDR_JTX_PLL_RC

Control bus address select.

0x0

R/W

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