AD9083BBCZ datasheet(32/93 Pages) AD

32 / 93 page

AD9083

Data Sheet

Rev. 0 | Page 32 of 93

CLOCK INPUTS

The AD9083 ADC sample clock is generated by using the

on-chip, integrated, integer PLL VCO by providing a reference

clock signal to the CLK± differential inputs (Pin K3 and

Pin J3). Clock multiplying employs the on-chip ADC PLL that

accepts a reference clock operating at a submultiple of the

desired ADC sample rate. The operating range of the clock

multiplier reference input is 50 MHz to 500 MHz. The PLL

then multiplies the reference clock up to the desired ADC

sample clock frequency, which generates all the clocks within

the AD9083. The block diagram of the on-chip PLL is shown in

Figure 68.

The AD9083 contains a low jitter, differential clock receiver

that is capable of interfacing directly to a differential clock

source. The input is self biased with a nominal impedance of

100 Ω. It is recommended that the clock source be ac-coupled

to the CLK± input pins. Improved phase noise performance

can be achieved with a higher clock input level. The quality of

the clock source, as well as its interface to the AD9083 clock

input, directly impacts ac performance. Select the phase noise

and spur characteristics of the clock source to meet the target

application requirements. The typical phase noise performance

of the on-chip PLL when clocking the AD9083 at a 2 GHz

sample rate is shown in Figure 67.

–85

–90

–95

–100

–105

–110

–115

–120

–125

–130

–135

–140

–145

–150

–155

–160

–165

10k

100k

10M

FREQUENCY (Hz)

INTEGRATED JITTER = 148.2

fS rms

Figure 67. AD9083 On-Chip PLL Phase Noise vs. Frequency Offset, 2 GHz ADC

Sample Rate, On-Chip DDC Enabled

For optimal performance of the on-chip PLL, connect a low

ESR, low ESL, X7R dielectric, 2.2 µF capacitor between the

REG_VCO pin and GND. Additionally, connect a C0G or NP0

dielectric, 33 nF capacitor between the VCOARSE_VCO pin

and GND. Place these capacitors as close to the AD9083 chip as

possible to avoid any external noise coupling.

PFD

÷R

CAL

172kΩ

100Ω

CLK+

PCB

CHIP

CLK–

30Ω

172kΩ

VCM

FILTER

OUTPUT

DIVIDER

CONTROL

÷D

REGULATOR

ADC_CLK

1GHz TO 2GHz

8.8GHz TO 12.4GHz

AVDD1P8

2.2µF

REG VCO

÷N

÷P

33nF

VCOARSE VCO

PCB

CHIP

Figure 68. AD9083 Clock Path Block Diagram

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