AD9083BBCZ datasheet(47/93 Pages) AD

47 / 93 page

Data Sheet

AD9083

Rev. 0 | Page 47 of 93

Initial Lane Alignment Sequence (ILAS)

The ILAS phase follows the CGS phase and begins on the next

LMFC boundary after SYNCINB± deassertion. The ILAS

consists of four mulitframes, with an /R/ character marking the

beginning and an /A/ character marking the end. The ILAS

begins by sending an /R/ character followed by 0 to 255 ramp

data for one multiframe. On the second multiframe, the link

configuration data is sent, starting with the third character. The

second character is a /Q/ character to confirm that the link

configuration data follows. All undefined data slots are filled

with ramp data. The ILAS sequence is never scrambled.

The ILAS sequence construction is shown in Figure 87. The

four multiframes include the following:

•

Multiframe 1 begins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

•

Multiframe 2 begins with an /R/ character followed by a

/Q/ character (/K28.4/), followed by link configuration

parameters over 14 configuration octets (see Table 23) and

ends with an /A/ character. Many of the parameter values

are of the value – 1 notation.

•

Multiframe 3 begins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

•

Multiframe 4 begins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

User Data and Error Detection

After the initial lane alignment sequence is complete, the user

data (ADC samples) is sent. During transmission of the user data,

a mechanism called character replacement monitors the frame

clock and multiframe clock alignment. This mechanism replaces

the last octet of a frame or multiframe with an /F/ or /A/

alignment characters when the data meets certain conditions.

These conditions are different for unscrambled and scrambled

data. The scrambling operation is enabled by default, but it can

be disabled using the SPI.

For scrambled data, any 0xFC character at the end of a frame

is replaced by an /F/, and any 0x7C character at the end of a

multiframe is replaced with an /A/. The JESD204B receiver

(Rx) checks for /F/ and /A/ characters in the received data

stream and verifies that they only occur in the expected

locations. If an unexpected /F/ or /A/ character is found, the

receiver handles the situation by using dynamic realignment or

asserting the SYNCINB± signal for more than four frames to

initiate a resynchronization. For unscrambled data, if the final

octet of two subsequent frames are equal, the second octet is

replaced with an /F/ symbol if it is at the end of a frame, and an

/A/ symbol if it is at the end of a multiframe.

Insertion of alignment characters can be modified using SPI. The

frame alignment character insertion (FACI) is enabled by default.

8-Bit/10-Bit Encoder

The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols

and inserts control characters into the stream when needed. The

control characters used in JESD204B are shown in Table 23.

The 8-bit/10-bit encoding ensures that the signal is dc balanced by

using the same number of ones and zeros across multiple symbols.

The 8-bit/10-bit interface has options that can be controlled via

the SPI. These operations include bypass and invert. These options

are troubleshooting tools for the verification of the digital front

end (DFE). Refer to the Memory Map section, Register 0x2A3

(JTX_DL_204B_CONFIG0) for information on configuring the

8-bit/10-bit encoder.

END OF

MULTIFRAME

START OF

ILAS

START OF LINK

CONFIGURATION DATA

START OF

USER DATA

Figure 87. Initial Lane Alignment Sequence

Table 23. AD9083 Control Characters Used in JESD204B

Abbreviation

Control Symbol

8-Bit Value

10-Bit Value,

RD1 = −1

10-Bit Value,

RD1 = +1

Description

/R/

/K28.0/

000 11100

001111 0100

110000 1011

Start of multiframe

/A/

/K28.3/

011 11100

001111 0011

110000 1100

Lane alignment

/Q/

/K28.4/

100 11100

001111 0100

110000 1101

Start of link configuration data

/K/

/K28.5/

101 11100

001111 1010

110000 0101

Group synchronization

/F/

/K28.7/

111 11100

001111 1000

110000 0111

Frame alignment

RD means running disparity.

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