AD9083BBCZ datasheet(28/93 Pages) AD

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AD9083

Data Sheet

Rev. 0 | Page 28 of 93

THEORY OF OPERATION

ADC ARCHITECTURE

The AD9083 is a 16-channel, highly integrated and programmable

front-end digitizer for a wide range of applications.

The AD9083 ADC uses a first-order, CTSD modulator

architecture that provides first-order quantization noise shaping

and inherent first-order, sinc shaped, antialias filtering. This

oversampling, combined with the inherent antialias filtering,

eliminates thermal noise folding into the band of interest. This

feature enables a fast signal settling time when compared to the

settling time of Nyquist rate converters, which require highly

selective antialias filters to eliminate noise folding. The first-

order Σ-Δ modulator is superior to a higher order modulator

because the former requires only a second-order CIC decimation

filter to eliminate quantization noise before decimation. This

low order decimation filter features better signal settling time

compared to a higher order filter. Built into the ADC front end

is a programmable termination resistor, programmable gain

adjust, and a programmable, single-pole, low-pass filter (LPF).

Background calibration digitally calibrates signal path gain

error and nonlinearity. The ADC noise density is shaped, not

flat, and is better at lower bandwidths. The worst case ADC

noise density at a 2 GHz sample rate and 100 MHz offset is

−147 dBFS/Hz. For a 2 GSPS sample rate and at 100 MHz

bandwidth, the input referred noise figure is only 0.1 dB with

40 dB of front-end gain.

Flicker noise may be higher for this architecture, lending itself

to better performance for IF applications instead of zero IF.

Similarly, input referred offset has no effect on an IF application,

except when using the full dynamic range of the signal

converter. A low power mode is available with a noise density

increase of 3 dB for half the converter power.

The ADC in the AD9083 must be initialized and set up based

on the particular use case. Figure 55 shows the block diagram of

the ADC used in the AD9083. The ADC in the AD9083

requires a set of user-defined variables that set up the ADC in

the use case specified by the application. These variables are as

follows:

•

fS, the sample clock of the converter core (1.0 GSPS to

2.0 GSPS).

•

VMAX, the differential peak-to-peak input full scale

(0.5 V p-p, differential, to 2.0 V p-p, differential).

•

fC, the cutoff frequency of the LPF (125 MHz to 800 MHz).

•

RTERM, the differential input termination resistance.

•

fINMAX, the maximum input signal frequency.

•

Backoff, the reduction in front-end gain for increased

linearity.

•

EN_HP, which increases the SNR by 2.5 dB by doubling

the ADC power dissipation.

RTERM

VINx+

x = 1 TO 16

Σ-Δ

MODULATOR

R/2

fC = 125MHz TO 800MHz

VMAX

VINx–

R/2

Figure 55. AD9083 ADC Block Diagram

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