AD9083BBCZ datasheet(63/93 Pages) AD

63 / 93 page

Data Sheet

AD9083

Rev. 0 | Page 63 of 93

Addr.

Name

Bits

Bit Name

Description

Reset Access

TOPREF_PIN_CTRL

For TOP REF.

1: PD Pin and MASK Bit Control

0: CONFIG Bit Programming Control

0x0

R/W

CLKTOP_PIN_CTRL

Power Down for CLKTOP.

1: PD Pin and MASK Bit Control

0: CONFIG Bit Programming Control

0x0

R/W

ADC_PIN_CTRL

For All 16 ADCs.

1: PD Pin and MASK Bit Control

0: CONFIG Bit Programming Control

0x0

R/W

0x31

LOW_PWR_PIN_

POLARITY

[7:2]

RESERVED

Reserved.

0x0

[1:0]

POL

Polarity of PD Pin.

0: Active High.

1: Active Low.

0x0

R/W

0x32

LOW_PWR_CONFIG

[7:6]

RESERVED

Reserved.

0x0

JTXPHY_LP_MODE

Low Power Mode for JTXPHY.

0 : Normal Mode.

1 : Low Power Mode.

0x0

R/W

JTX_LP_MODE

Low Power Mode for JTX.

0: Normal Mode

1: Low Power Mode

0x0

R/W

DIG_DP_LP_MODE

Low Power Mode for Digital Datapath.

0: Normal Mode

1: Low Power Mode

0x0

R/W

TOPREF_LP_MODE

Low Power Mode for Top Ref. If 1 then bias

currents to on-chip PLL, ADC, clock buffer and

monitor mux from master bias are disabled. BG is

still active.

0: Normal Mode

1: Low Power Mode

0x0

R/W

CLKTOP_LP_MODE

Low Power Mode for Clock Top.

0: Normal Mode

1: Low Power Mode

0x0

R/W

ADC_LP_MODE

Low Power Mode for All 16 ADCs.

0: Normal Mode

1: Low Power Mode

0x0

R/W

0x33

LOW_PWR_PIN_MASK

[7:6]

RESERVED

Reserved.

0x0

JTXPHY_LP_PIN_MASK

Mask the PD to JTXPHY.

0: Mask

1: Unmask

0x0

R/W

JTX_LP_PIN_MASK

Mask the PD to JTX.

0: Mask

1: Unmask

0x0

R/W

DIG_DP_LP_PIN_MASK

Mask the PD to DIG_DP.

0: Mask

1: Unmask

0x0

R/W

TOPREF_LP_PIN_MASK

Mask the PD to TOP REF.

0: Mask

1: Unmask

0x0

R/W

CLKTOP_LP_PIN_MASK

Mask the PD to CLKTOP.

0: Mask

1: Unmask

0x0

R/W

ADC_LP_PIN_MASK

Mask the PD to ADC

0: Mask

1: Unmask.

0x0

R/W

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