AD9083BBCZ datasheet(52/93 Pages) AD

tên linh kiện	AD9083BBCZ

Giải thích chi tiết về linh kiện	16-Channel, 125 MHz Bandwidth, JESD204B Analog-to-Digital Converter

PDF	93 Pages

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52 / 93 page

AD9083

Data Sheet

Rev. 0 | Page 52 of 93

Key Features and Notes Regarding Resynchronization

Mode

In SYSREF resynchronization mode, all clocks shut down and

restart in-phase to the SYSREF pulse.

The JESD LMFC aligns at a deterministic phase/delay from the

SYSREF pulse.

The NCOs reset at a deterministic time after the SYSREF pulse

is received. The NCO reset occurs after the datapath clocks are

aligned to the new SYSREF.

The latency numbers, such as SYSREF LMFC delay, SYSREF to

NCO reset delay, and so on, depend on the configuration used.

The latency of the NCO reset from SYSREF is constant for all

periodic SYSREF pulses. If the SYSREF period is altered, a

resynchronization followed by an NCO reset is triggered.

The SYSREF period for any mode must be a multiple of the

multiframe clock period. Additional restriction may be

required due to decimation modes.

An LMFC settling period of 8 LMFCs is expected for the

internal LMFC to stabilize after a SYSREF input initiates

realignment.

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