AD9083BBCZ datasheet(33/93 Pages) AD

33 / 93 page

Data Sheet

AD9083

Rev. 0 | Page 33 of 93

POWER MODES

The AD9083 features low power modes that enable powering

down certain blocks of the AD9083, or the entire chip, based on

trade-offs between power saving achieved and wake-up time to full

power on. These sections discuss the power-down modes available

within the AD9083. All modes are controlled via the SPI.

Full Power-Down Mode

In full power-down mode, almost all of the blocks within the

AD9083 are held in low power mode, resulting in the highest

power saving. However, this power saving results in slow wake-

up times. The ADC internal reference, on-chip clock PLL, and

the JESD204B PLL are powered on. On release of this mode, the

ADC must undergo recalibration. The on-chip clock PLL and

the JESD204B PLL must undergo relocking to achieve normal

performance.

Standby Mode

In standby mode, some of the blocks are kept running while

others are held in a clock gated mode, resulting in medium

power saving, but faster wake-up time compared to full power-

down mode. The ADC cores, on-chip clock PLL, JESD204B

PLL, and digital outputs are kept powered on. The digital and

JESD204B framer blocks are clock gated. The JESD204B link

must be reinitialized on release of this mode.

Power-On Mode

Power-on mode is the normal operation mode for the AD9083.

All blocks within the AD9083 are powered up and running at

rated frequency. However, to further reduce power during

normal operation, digital portions that do not need to be

running can be selectively clock gated. For example, if the

application only requires one numerically controlled oscillator

(NCO)/mixer, the other two NCOs/mixers can be disabled. The

same principle applies to the JESD204B lanes. The unused lanes

can be powered down.

TEMPERATURE DIODE

The AD9083 contains diode-based temperature sensors. The

output voltages of these diodes correspond to the temperature

of the silicon. There is a pair of diodes, one of which is 20× the

size of the other. It is recommended to use both diodes to

obtain an accurate estimate of the die temperature. For more

information, see the AN-1432 Application Note, Practical

Thermal Modeling and Measurements in High Power ICs. The

temperature diode voltages can be exported to the TD pin using

the SPI (see Figure 69).

AVDD1P8

1x DIODE

VOLTAGE

20x DIODE

VOLTAGE

TEMPERATURE

DIODE SELECT

TEMPERATURE

DIODE

ENABLE

GND

Figure 69. TD Pin Using the SPI

DIGITAL SIGNAL PROCESSING OVERVIEW

The CTSD ADC includes a digital processing block between the

CTSD ADC output and the JESD204 transmitter core. The

digital signal processing block can filter and translate IF to zero

IF signals suitable for post processing by the host without any

loss of dynamic range. This block includes a programmable

CIC decimation filter, a mixer with NCO, and a highly

programmable, multistage decimation FIR filter. Figure 70

shows a simplified diagram of the digital functional block. For

clarity, Figure 70 does not show the digital datapath routing

options, which are described in the Signal Processing Tile

section.

FIR

DDC

NCO

CIC

LOW-PASS

CTSD

Figure 70. Simplified Diagram of the Digital Functional Block

The CTSD ADC provides a highly oversampled digital output

representing the desired IF signal pass band and the out-of-

band shaped noise. Figure 71 shows the spectrum of the raw

ADC output.

DESIRED

INPUT

BAND OF

INTEREST

fS/64

fS/16

fS/2

ADC NOISE

ADC DATA OUTPUT

fIN

Figure 71. Spectrum of the Raw ADC Output

The digital signal path first filters and decimates the ADC

output data by Nx. It is necessary to remove the majority of the

out of band quantization noise before any clock rate reduction

or frequency translation. Figure 72 shows the decimator output

frequency spectrum.

fS/64

fIN

fS/16

fS/2N

DECIMATED DATA OUTPUT

Figure 72. Frequency Spectrum of the Decimator Output

Next, the DDC can be enabled to perform a frequency

translation. Typically, this frequency translation is from a

middle IF down to zero IF or very low IF. Figure 73 shows a

representative of the output spectrum of the DDC output.

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