AD9083BBCZ datasheet(75/93 Pages) AD

75 / 93 page

Data Sheet

AD9083

Rev. 0 | Page 75 of 93

Addr.

Name

Bits

Bit Name

Description

Reset Access

0x1C5 DDC_SYNC_STATUS

[7:1]

RESERVED

Reserved.

0x0

DDC_SYNC_EN_CLEAR

DDC Sync Enable Clear Status. DDC Sync Enable

Clear Status

0x0

JESD204B Transmitter (JTX) Control Registers

0x200

0x25F

by 1

JTX_CORE_SAMPLE_

XBARn

JTX_CONV_DISABLE

Converter sample mask to 0.

0x0

R/W

[6:0]

JTX_CONV_SEL

Converter sample crossbar selection.

0x0

R/W

0x260 JTX_CORE_CONFIG

JTX_SYSREF_FOR_RELINK

Will mask lane data to 0 until another SYSREF

pulse is received if SYNC~ is asserted. Applies to

JESD204B operation only.

0x0

R/W

JTX_SYSREF_FOR_STARTUP

Will mask lane data to 0 until the first SYSREF

pulse is received after reset.

0x0

R/W

[5:4]

RESERVED

Reserved.

0x0

JTX_CHKSUM_LSB_ALG

0: Sum whole octets of L0 config for checksum 1:

Sum individual fields for checksum.

0x0

R/W

JTX_CHKSUM_DISABLE

Checksum is always 0.

0x0

R/W

[1:0]

JTX_LINK_TYPE

Link layer type selection: 0: 204B 1: 204C 2: 204H. 0x0

R/W

0x261

0x264

by 1

JTX_CORE_LANE_

XBARn

JTX_LANE_PD

Physical lane in use based on link and crossbar

configuration.

0x0

JTX_FORCE_LANE_PD

Send 0s and activate jtx_lane_pd.

0x0

R/W

JTX_LANE_INV

Invert logical lane data (before crossbar).

0x0

R/W

[4:0]

JTX_LANE_SEL

Lane crossbar selection. Setting here selects

which logical lane should feed the physical lane.

0x0

R/W

0x271 JTX_CORE_TEST_

CONFIG

JTX_TEST_USER_GO

Activate USER_SINGLE test mode.

0x0

R/W

JTX_TEST_MIRROR

Reverse bit order of test data.

0x0

R/W

[5:4]

JTX_TEST_GEN_SEL

Test insertion point.

0x0

R/W

[3:0]

JTX_TEST_GEN_MODE

Test mode selection.

0: Disabled for TEST_GEN_SEL = 0, lane loopback

for TEST_GEN_SEL = 1.

1: CHECKER_BOARD

2: WORD_TOGGLE

3: PN31

5: PN15

7: PN7

8: RAMP

14: USER_REPEAT

15: USER_SINGLE.

0x0

R/W

0x272 JTX_TEST_USER_DATA0 [7:0]

JTX_TEST_USER_DATA[7:0]

User defined test data in LSBs.

0x0

R/W

0x273 JTX_TEST_USER_DATA1 [7:0]

JTX_TEST_USER_DATA[15:8]

User defined test data in LSBs.

0x0

R/W

0x274 JTX_TEST_USER_DATA2 [7:0]

JTX_TEST_USER_DATA[23:16] User defined test data in LSBs.

0x0

R/W

0x275 JTX_TEST_USER_DATA3 [7:0]

JTX_TEST_USER_DATA[31:24] User defined test data in LSBs.

0x0

R/W

0x276 JTX_TEST_USER_DATA4 [7:0]

JTX_TEST_USER_DATA[39:32] User defined test data in LSBs.

0x0

R/W

0x277 JTX_TEST_USER_DATA5 [7:0]

JTX_TEST_USER_DATA[47:40] User defined test data in LSBs.

0x0

R/W

0x278 JTX_TEST_USER_DATA6 [7:0]

JTX_TEST_USER_DATA[55:48] User defined test data in LSBs.

0x0

R/W

0x279 JTX_TEST_USER_DATA7 [7:0]

JTX_TEST_USER_DATA[63:56] User defined test data in LSBs.

0x0

R/W

0x27A JTX_TEST_USER_DATA8 [7:2]

RESERVED

Reserved.

0x0

[1:0]

JTX_TEST_USER_DATA[65:64] User defined test data in LSBs.

0x0

R/W

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