AD9083BBCZ datasheet(62/93 Pages) AD

62 / 93 page

AD9083

Data Sheet

Rev. 0 | Page 62 of 93

Addr.

Name

Bits

Bit Name

Description

Reset Access

0x0A

CHIP_SCRATCH

[7:0]

CHIP_SCRATCH

Chip Scratchpad Register. This register is used to

provide a consistent memory location for

software debug.

0x0

R/W

0x0C

VENDOR_ID_LSB

[7:0]

CHIP_VENDOR_ID[7:0]

Vendor ID.

0x56

0x0D

VENDOR_ID_MSB

[7:0]

CHIP_VENDOR_ID[15:8]

Vendor ID.

0x4

0x20

PORB_STAT

RESERVED

Reserved.

0x0

PORB_VDDSYNTH_JTX_PLL_1

PORb Status of JESD PLL 1.0 V VDD.

0x0

PORB_VDDPHY_SER_1P0

PORb Status of JESD SER PHY 1.0 V VDD.

0x0

PORB_VDDLDO_JTX_PLL_

1P8

PORb Status of JESD PLL (LDO) 1.8 V VDD.

0x0

PORB_VDDCP_JTX_PLL_1P0

PORb Status of JESD PLL 1.0 V VDD.

0x0

PORB_VDD_SYNCRX_1P8

PORb Status for SYNCRX I/O VDD 1.8V.

0x0

PORB_VDD_DIG_1P0

PORb Status of Digital 1.0 V VDD and Digital I/O

1.8 V VDD.

0x0

PORB_VDD_ANA

Status of VDD Domains in ADC, CLKTOP, on-chip

PLL, and TOPREF.

0x0

0x21

PORB_MASK_RESET

[7:1]

RESERVED

Reserved.

0x0

PORB_IGNORE

Controls Whether or Not to Gate Internal Resets

with PORb.

0x0

R/W

0x24

BLOCK_RESET

[7:6]

RESERVED

Reserved.

0x0

DIG_DP_JTX_RESET

Resets the DIG Datapath and JTX.

1: Assert Reset.

0: De-Assert Reset

0x0

R/W

JTX_PLL_RESET

Reset the JTX_PLL.

1: Assert Reset.

0: De-Assert Reset.

0x0

R/W

JTXPHY_RESET

Reset the SER PHY.

1: Assert Reset.

0: De-Assert Reset.

0x0

R/W

TOPREF_RESET

Reset the TOP REF.

1: Assert Reset.

0: De-Assert Reset.

0x0

R/W

CLKTOP_RESET

Reset the CLK TOP.

1: Assert Reset.

0: De-Assert Reset.

0x0

R/W

ADC_RESET

Reset the ADCs.

1: Assert Reset.

0: De-Assert Reset.

0x0

R/W

0x30

LOW_PWR_PIN_CTRL

[7:6]

RESERVED

Reserved.

0x0

JTXPHY_PIN_CTRL

For JTXPHY.

1: PD Pin and MASK Bit Control

0: CONFIG Bit Programming Control

0x0

R/W

JTX_PIN_CTRL

For JTX.

1: PD Pin and MASK Bit Control

0: CONFIG Bit Programming Control

0x0

R/W

DIG_DP_PIN_CTRL

For DIG DP.

1: PD Pin and MASK Bit Control

0: CONFIG Bit Programming Control

0x0

R/W

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