AD9083BBCZ datasheet(78/93 Pages) AD

78 / 93 page

AD9083

Data Sheet

Rev. 0 | Page 78 of 93

Addr.

Name

Bits

Bit Name

Description

Reset Access

0x2A4 JTX_DL_204B_CONFIG1 [7:3]

RESERVED

Reserved.

0x0

JTX_DL_204B_LSYNC_EN_

CFG

Lane sync on both sides enabled.

0x0

R/W

JTX_DL_204B_DEL_SCR_CFG Alternative scrambler enable (see JESD204B

section 5.2.4) 1 = scrambling begins at octet 2 of

user data 0 = scrambling begins at octet 0 of user

data This is the common usage.

0x0

R/W

JTX_DL_204B_10B_MIRROR

Reverse order of 10 bit symbols from 204B link

layer data.

0x0

R/W

0x2A5 JTX_DL_204B_CONFIG2 [7:6]

RESERVED

Reserved.

0x0

JTX_DL_204B_TESTMODE_IG

NORE_SYNCN_CFG

ignore sync_n input during D21.5 and RPAT

modes.

0x0

R/W

JTX_DL_204B_TPL_TEST_EN_

CFG

Turn on JESD Pattern Sequence test mode.

0x0

R/W

RESERVED

Reserved.

0x0

[2:1]

JTX_DL_204B_RJSPAT_SEL_C

High Frequency Patterns Test Modes 11 =

Unused 10 = JTSPAT Sequence 01 = JSPAT

Sequence 00 = RPAT Sequence.

0x0

R/W

JTX_DL_204B_RJSPAT_EN_CF

Enable RPAT/JSPAT/JTSPAT Generator 1 = on

(Note: Must also set phy_data_sel[n] = 1) 0 = off.

0x0

R/W

0x2A6 JTX_DL_204B_KF_ILAS [7:0]

JTX_DL_204B_KF_ILAS_CFG

Number of multiframes to transmit during

initialization sequence = 4*(kf_ilas_cfg+1).

0x0

R/W

0x2A8 JTX_DL_204B_SYNC_N 7

JTX_DL_204B_SYNC_N

JESD204 Frame Sync. Active low. Synchronous

upon rising edge pclk. 0=transmit code group

sync (K characters). Subclass 1: Internal LMFC

reset for 1-pclk by falling edge sync_n Subclass 0:

Internal lmfc held in reset by sync_n=0.

0x0

[6:2]

RESERVED

Reserved.

0x0

JTX_DL_204B_SYNC_N_

FORCE_EN

Force SYNC~ signal to value specified.

0x0

R/W

JTX_DL_204B_SYNC_N_

FORCE_VAL

Value to force SYNC~ if force enabled.

0x0

R/W

0x2A9 JTX_DL_204B_CLEAR_

SYNC_NE_COUNT

[7:1]

RESERVED

Reserved.

0x0

JTX_DL_204B_CLEAR_SYNC_

NE_COUNT

Clear counter of SYNC~ falling edges.

0x0

R/W

0x2AA JTX_DL_204B_SYNC_

NE_COUNT

[7:0]

JTX_DL_204B_SYNC_NE_COU

Count of falling SYNC~ edges.

0x0

0x2AB

0x2AE

by 1

JTX_DL_204B_LANE_

CONFIGn

[7:5]

RESERVED

Reserved.

0x0

JTX_DL_204B_SCR_IN_CTRL_

CFG

connect test_data[39:0] to scrambler input for

lane n.

0x0

R/W

JTX_DL_204B_SCR_DATA_

SEL_CFG

Scrambler Input JESD Data on Lane Boundary

scr_data_sel_cfg [n]: 1 = Continuous D21.5 Data

for Lane [n] scr_data_sel_cfg [n]: 0 = JESD Frame

Memory or ILAS Data for Lane[n].

0x0

R/W

JTX_DL_204B_PHY_DATA_

SEL_CFG

JESD Data to PHY on a Lane Boundary [n]:

1 = RPAT/JSPAT/JTSPAT Generator Data [n]:

0 = 8-bit/10-bit Encoder Output Data.

0x0

R/W

RESERVED

Reserved.

0x0

RESERVED

Reserved

0x0

R/W

0x2C9

0x2CC

by 1

JTX_PHY_IFX_LANE_

CONFIGn

[7:4]

JTX_LANE_FIFO_WR_ENTRIES Number of entries in the FIFO synchronized to

the write pointer.

0x0

[3:0]

JTX_BR_LOG2_RATIO

Log(bit repeat ratio)/Log(2), per lane.

0x0

R/W

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