AD9083BBCZ datasheet(82/93 Pages) AD

82 / 93 page

AD9083

Data Sheet

Rev. 0 | Page 82 of 93

Addr.

Name

Bits

Bit Name

Description

Reset Access

0x413 PRE_TAP_LEVEL_CH0

[7:0]

DRVPREEM_CH0_SER_RC

Sets Pre Tap Level for SERDOUT0.

0 = 0 dB.

1 = 3 dB.

2 = 6 dB.

3 = not applicable.

0x0

R/W

0x414 PRE_TAP_LEVEL_CH1

[7:0]

DRVPREEM_CH1_SER_RC

Sets Pre Tap Level for SERDOUT1.

0 = 0 dB.

1 = 3 dB.

2 = 6 dB.

3 = not applicable.

0x0

R/W

0x415 PRE_TAP_LEVEL_CH2

[7:0]

DRVPREEM_CH2_SER_RC

Sets Pre Tap Level for SERDOUT2.

0 = 0 dB.

1 = 3 dB.

2 = 6 dB.

3 = not applicable.

0x0

R/W

0x416 PRE_TAP_LEVEL_CH3

[7:0]

DRVPREEM_CH3_SER_RC

Sets Pre Tap Level for SERDOUT3.

0 = 0 dB.

1 = 3 dB.

2 = 6 dB.

3 = not applicable.

0x0

R/W

0x425 PARITY_ERROR

[7:0]

PARITY_ERROR_SER[7:0]

JTx Parity Output Error flag, <0>=ch0, <1>=ch1 0x0

0x426 PARITY_ERROR2

[7:0]

PARITY_ERROR_SER[15:8]

JTx Parity Output Error flag, <0>=ch0, <1>=ch1 0x0

0x427 PARITY_RST_N

[7:0]

SER_PARITY_RST_N[7:0]

JTx Parity Clear bit each bit is a channel. JTx

Parity Clear bit each bit is a channel ==> <3> =

chan_3, <2> = chan_2

0x0

R/W

0x428 PARITY_RST_N2

[7:0]

SER_PARITY_RST_N[15:8]

JTx Parity Clear bit each bit is a channel. JTx

Parity Clear bit each bit is a channel ==> <3> =

chan_3, <2> = chan_2

0x0

R/W

0x439 MAIN_DATA_INV

[7:4]

RESERVED

Reserved

0x0

R/W

OUTPUTDATAINVERT_CH3

JTx, Invert SERDOUT3 data.

0 = normal.

1 = invert.

0x0

R/W

OUTPUTDATAINVERT_CH2

JTx, Invert SERDOUT2 data.

0 = normal.

1 = invert.

0x0

R/W

OUTPUTDATAINVERT_CH1

JTx, Invert SERDOUT1 data.

0 = normal.

1 = invert.

0x0

R/W

OUTPUTDATAINVERT_CH0

JTx, Invert SERDOUT0 data.

0 = normal.

1 = invert.

0x0

R/W

0x447 SYNCINB_CTRL

[7:4]

RESERVED

Reserved.

0x0

PD_SYNCINB_RX_RC

SYNCINB receiver power control bit.

0 = Normal Operation

1 = Power Down

0x1

R/W

SYNCINB_RX_PN_INV_RC

SYNCINB Polarity control bit.

0 = Normal polarity

1 = Invert polarity

0x0

R/W

SYNCINB_RX_ONCHIP_TERM_R

SYNCINB onchip termination control bit.

0 = Disabled (Use if 0x447[0] = 0)

1 = Enabled (100Ω differential)

0x0

R/W

SYNCINB_RX_MODE_RC

SYNCINB Mode control bit.

0 = CMOS mode (Single Ended)

1 = LVDS mode (Differential)

0x0

R/W

0x449 JTX_CTRL

[7:1]

RESERVED

Reserved.

0x0

JTAG_EN_SER_TESTMODE_RC SYNC control bit.

0x0

R/W

AD9083BBCZ bảng dữ liệu(PDF) 82 Page - Analog Devices

AD9083BBCZ bảng dữ liệu(HTML) 82 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

bảng dữ liệu tải về

Link URL