| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
AD9083BBCZ bảng dữ liệu(PDF) 77 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9083BBCZ bảng dữ liệu(HTML) 77 Page - Analog Devices |
|
77 / 93 page ![]() Data Sheet AD9083 Rev. 0 | Page 77 of 93 Addr. Name Bits Bit Name Description Reset Access 0x289 JTX_L0_SCR_L 7 JTX_SCR_CFG JTx Scrambler 0 = Disabled 1 = Enabled 0x0 R/W [6:5] RESERVED Reserved. 0x0 R [4:0] JTX_L_CFG Number of lanes per converter device (link). 0 : L = 1 1 : L = 2 2 : L = 3 3 : L = 4 Values > 3 are not supported 0x0 R/W 0x28A JTX_L0_F [7:0] JTX_F_CFG Number of octets per frame per lane. F = N/16 × M × N / L. 0x0 R/W 0x28B JTX_L0_K [7:0] JTX_K_CFG Number of frames in a multi-frame/block. 0x0 R/W 0x28C JTX_L0_M [7:0] JTX_M_CFG Number of converters per device. JTx number of virtual converters per link (M=JTX M configuration + 1). 0 = 1 virtual converter 1 = 2 virtual converters 2 = 3 virtual converters 3 = 4 virtual converters 5 = 6 virtual converters 7 = 8 virtual converters 11 = 12 virtual converters 15 = 16 virtual converters All other values are invalid. 0x0 R/W 0x28D JTX_L0_CS_N [7:6] JTX_CS_CFG Number of control bits per sample. 0x0 R/W 5 RESERVED Reserved. 0x0 R [4:0] JTX_N_CFG Converter resolution. 0x0 R/W 0x28E JTX_L0_SUBCLASSV_NP [7:5] JTX_SUBCLASSV_CFG Device Subclass Version 2: align transmission and LMFC boundaries to SYNC~ 1: align transmission and LMFC boundaries to SYSREF 0: transmission and LMFC boundaries are arbitrary. 0x0 R/W [4:0] JTX_NP_CFG Total number of bits per sample. 0x0 R/W 0x28F JTX_L0_JESDV_S [7:5] JTX_JESDV_CFG JESD204 version 001: JESD204B 0x0 R/W [4:0] JTX_S_CFG Samples per converter per frame. 0x0 R/W 0x290 JTX_L0_HD 7 JTX_HD_CFG High Density format enabled. 0x0 R/W [6:0] RESERVED Reserved. 0x0 R 0x293 to 0x296 by 1 JTX_L0_CHKSUMn [7:0] JTX_CHKSUM_CFG Checksum calculation output (per lane). 0x0 R 0x297 to 0x29A by 1 JTX_L0_LIDn [7:5] RESERVED Reserved. 0x0 R [4:0] JTX_LID_CFG Lane identification number (within link). 0x0 R/W 0x2A3 JTX_DL_204B_CONFIG0 [7:4] JTX_DL_204B_ILAS_DELAY_C FG Delays ILAS Start by 0 to 15 LMFC Periods. 0x0 R/W 3 JTX_DL_204B_BYP_ILAS_CFG bypass initial lane alignment sequence. 0x0 R/W 2 JTX_DL_204B_ILAS_TEST_ EN_CFG Enable ilas test mode that sends repeated ILAS pattern. If sync_n not active then 16 Kchars sent followed by repeated ILAS. 0x0 R/W 1 JTX_DL_204B_BYP_8B10B_ CFG Bypass 8-bit/10-bit encoder. 0x0 R/W 0 JTX_DL_204B_BYP_ACG_CFG bypass alignment character generation. 0x0 R/W |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |