845GL datasheet(111/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

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Functional Description

4.3

AGP Interface

See the Accelerated Graphics Port Interface Specification, Revision 2.0 for additional details about

the AGP interface.

4.3.1

Overview

The GMCH multiplexes an AGP interface with two DVO ports. The DVO ports can support single

channel DVO devices or can combine to support dual-channel devices, supporting higher

resolutions and refresh rates. When an external AGP device is used, the multiplexed DVO ports are

not available, as the GMCH’s IGD will be disabled. For more information on the multiplexed DVO

interface, refer to Section 4.5.

The GMCH supports 1.5 V AGP 1X/2X/4X devices. The AGP signal buffers have one mode of

operation; 1.5 V drive/receive (not 3.3 V tolerant). The GMCH supports 4X (266 MT/s) clocking

transfers for read and write data, and sideband addressing. The GMCH has a 32-deep AGP request

queue.

AGP semantic transactions to system SDRAM do not get snooped and are, therefore, not coherent

with the processor caches. PCI semantic transactions on AGP to system SDRAM are snooped.

AGP semantic accesses to the hub interface/PCI are not supported. PCI semantic accesses from an

AGP master to hub interface are also not supported.

4.3.1.1

Lock Behavior

If the processor has established a lock to AGP, the GMCH immediately retries incoming FRAME#

cycles. The reads will not be processed internally as a delayed transaction.

If the processor has established a lock to another resource other than AGP, the GMCH will accept

incoming FRAME# cycles based on the other retry/disconnect rules. Since snoops cannot be

generated to the processor while a lock is outstanding, eventually the GMCH’s PCI interface backs

up.

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