845GL datasheet(42/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

3.2

Platform Configuration

In some previous chipsets the MCH (or GMCH) component and the I/O Controller Hub component

were physically connected by PCI bus #0. From a configuration standpoint, both components

appeared to be on PCI bus #0 which was also the system’s primary PCI expansion bus. The north

bridge contained two PCI devices while the south bridge was considered one PCI device with

multiple functions.

In the 845G chipset the configuration structure is significantly different. The GMCH and the ICH4

are physically connected by the hub interface; thus, from a configuration standpoint, the hub

interface is logically PCI bus #0. As a result, all devices internal to the GMCH and ICH4 appear to

be on PCI bus #0. The system’s primary PCI expansion bus is physically attached to the ICH4 and,

from a configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge

and therefore has a programmable PCI Bus number. The AGP appears to system software to be a

real PCI bus behind PCI-to-PCI bridges resident as devices on PCI bus #0.

Note: The primary PCI bus is referred to as PCI_A in this document and is not PCI bus #0 from a

configuration standpoint.

The GMCH contains the following PCI devices within a single physical component. The

configuration registers for the devices are mapped as devices residing on PCI bus #0.

• Device 0: Host-HI Bridge/DRAM controller. Logically this appears as a PCI device residing

on PCI bus #0. Physically Device 0 contains the standard PCI registers, DRAM registers, AGP

capabilities registers, the Graphics Aperture controller, and other GMCH specific registers.

• Device 1: Host-AGP Bridge. Logically this appears as a “virtual” PCI-to-PCI bridge residing

on PCI bus #0. Physically Device 1 contains the standard PCI-to-PCI bridge registers and the

standard AGP/PCI configuration registers (including the AGP I/O and memory address

mapping).

• Device 2: Integrated Graphics controller. Logically this appears as a PCI device residing on

PCI bus #0. Physically Device 2 contains the configuration registers for 3D, 2D and display

functions.

• Device 6: Intel Reserved.

Reserved

Bits

Some of the GMCH registers described in this chapter contain reserved bits. These bits are

labeled Reserved (Rsvd). Software must deal correctly with fields that are reserved. On reads,

software must use appropriate masks to extract the defined bits and not rely on reserved bits

being any particular value. On writes, software must ensure that the values of reserved bit

positions are preserved. That is, the values of reserved bit positions must first be read, merged

with the new values for other bit positions, and then written back. Note the software does not

need to perform read, merge, and write operations for the configuration address register.

Reserved

Registers

In addition to reserved bits within a register, the GMCH contains address locations in the

configuration space of the Host-Hub Interface Bridge entity that are marked either “Reserved” or

“Intel Reserved.” The GMCH responds to accesses to “Reserved” address locations by

completing the host cycle. When a “Reserved” register location is read, a zero value is returned.

(“Reserved” registers can be 8-, 16-, or 32-bits in size). Writes to “Reserved” registers have no

effect on the GMCH. Registers that are marked as “Intel Reserved” must not be modified by

system software. Writes to “Intel Reserved” registers may cause system failure. Reads to “Intel

Reserved” registers may return a non-zero value.

Default

Value upon

Reset

Upon Reset, the GMCH sets all of its internal configuration registers to predetermined default

states. Some register values at reset are determined by external strapping options. The default

state represents the minimum functionality feature set required to successfully bring up the

system. Hence, it does not represent the optimal system configuration. It is the responsibility of

the system initialization software (usually BIOS) to properly determine the DRAM configurations,

operating parameters and optional system features that are applicable, and to program the

GMCH registers accordingly.

Term

Description

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