845GL datasheet(96/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

3.5.3.6

CC—Class Code Register (Device 2)

Address Offset:

09h

−0Bh

Default Value:

030000h

Access:

Size:

24 bits

This register contains the device programming interface information related to the Sub-Class Code

and Base Class Code definition for the IGD. This register also contains the Base Class Code and

the function sub-class in relation to the Base Class Code.

3.5.3.7

CLS—Cache Line Size Register (Device 2)

Address Offset:

0Ch

Default Value:

00h

Access:

Size:

8 bits

The IGD does not support this register as a PCI slave.

3.5.3.8

MLT2—Master Latency Timer Register (Device 2)

Address Offset:

0Dh

Default Value:

00h

Access:

Size:

8 bits

The IGD does not support the programmability of the master latency timer because it does not

perform bursts.

Bit

Description

23:16

Base Class Code (BASEC).

03=Display controller

15:8

Sub-Class Code (SCC).

Function 0: 00h=VGA compatible or 80h=Non VGA; based on Device 0 GC bit 1.

Function 1: 80h=Non VGA;

7:0

Programming Interface (PI).

00h=Hardwired as a Display controller.

Bit

Description

7:0

Cache Line Size (CLS).

This field is hardwired to zeros. The IGD, as a PCI compliant master, does

not use the Memory Write and Invalidate command and, in general, does not perform operations

based on cache line size.

Bit

Description

7:0

Master Latency Timer Count Value.

Hardwired to zeros.

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