845GL datasheet(81/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

3.5.2.4

PCISTS1—PCI Status Register (Device 1)

Address Offset:

06–07h

Default Value:

00A0h

Access:

RO, R/WC

Size:

16 bits

PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with

primary side of the “virtual” PCI-to-PCI bridge embedded within the GMCH.

Bit

Description

Detected Parity Error (DPE)—RO.

Hardwired to 0. Parity is not supported on the primary side of

this device.

Signaled System Error (SSE)—R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set to 1 when GMCH Device 1 generates an SERR message over the hub interface

for any enabled Device 1 error condition. Device 1 error conditions are enabled in the

ERRCMD, PCICMD1 and BCTRL1 registers. Device 1 error flags are read/reset from the

ERRSTS and SSTS1 register.

Received Master Abort Status (RMAS)—RO.

Hardwired to 0. The concept of a master abort does

not exist on primary side of this device.

Received Target Abort Status (RTAS)—RO.

Hardwired to 0. The concept of a target abort does

not exist on primary side of this device. T

Signaled Target Abort Status (STAS)—RO.

Hardwired to 0. The concept of a target abort does not

exist on primary side of this device.

10:9

DEVSEL# Timing (DEVT)—RO.

Hardwired to 00. The GMCH does not support subtractive

decoding devices on bus 0. This bit field is therefore hardwired to 00 to indicate that Device 1 uses

the fastest possible decode.

Data Parity Detected (DPD)—RO.

Hardwired to 0. Parity is not supported on the primary side of

this device.

Fast Back-to-Back (FB2B)—RO.

Hardwired to 1. This indicates that the AGP/PCI_B interface

always supports fast back to back writes.

Reserved.

66/60MHz Capability (CAP66)—RO.

Hardwired to 1. The AGP/PCI bus is 66 MHz capable.

4:0

Reserved.

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