845GL datasheet(95/193 Pages) INTEL

95 / 193 page

Intel® 82845G/82845GL/82845GV GMCH Datasheet

3.5.3.4

PCISTS2—PCI Status Register (Device 2)

Address Offset:

06h

−07h

Default Value:

0090h

Access:

RO, R/WC

Size:

16 bits

PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and

PCI compliant target abort.

3.5.3.5

RID2—Revision Identification Register (Device 2)

Address Offset:

08h

Default Value:

See table below

Access:

Size:

8 bits

This register contains the revision number of the IGD.

Bit

Description

Detected Parity Error (DPE)—RO.

Hardwired to 0. IGD does not detect parity.

Signaled System Error (SSE)—RO.

Hardwired to 0. The IGD never asserts SERR#

Received Master Abort Status (RMAS)—RO.

Hardwired to 0. The IGD never gets a Master Abort.

Received Target Abort Status (RTAS)—RO.

Hardwired to 0. The IGD never gets a Target Abort.

Signaled Target Abort Status (STAS)—RO.

Hardwired to 0. The IGD does not use target abort

semantics.

10:9

DEVSEL# Timing (DEVT)—RO.

Hardwired to 00. Not applicable.

Data Parity Detected (DPD)—R/WC.

Hardwired to 0. Device 2 does not detect Parity Error

Responses (the IGD does not do parity detection).

Fast Back-to-Back (FB2B)—RO.

Hardwired to 1. The IGD accepts fast back-to-back when the

transactions are not to the same agent.

User Defined Format (UDF)—RO.

Hardwired to 0.

66 MHz PCI Capable (66C)—RO.

Hardwired to 0. Not applicable.

CAP LIST— RO.

Hardwired to 1. This indicates that the register at 34h provides an offset into the

function’s PCI Configuration Space containing a pointer to the location of the first item in the list.

3:0

Reserved.

Bit

Description

7:0

Revision Identification Number.

This is an 8-bit value that indicates the revision identification

number for the IGD.

82845G and 82845GL GMCH

01h = A1 Stepping

03h = B1 Stepping

82845GV GMCH

01h = A1 Stepping

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