845GL datasheet(89/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

3.5.2.19

PMBASE1—Prefetchable Memory Base Address Register (Device 1)

Address Offset:

24–25h

Default Value:

FFF0h

Access:

R/W

Size:

16 bits

This register controls the processor to PCI_B prefetchable memory accesses routing based on the

following formula:

PREFETCHABLE_MEMORY_BASE

≤ address ≤ PREFETCHABLE_MEMORY_LIMIT

The upper 12 bits of the register are read/write and correspond to the upper 12 address bits

A[31:20] of the 32-bit address. The bottom four bits of this register are read only and return zeros

when read. This register must be initialized by the configuration software. For the purpose of

address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory

address range will be aligned to a 1-MB boundary.

3.5.2.20

PMLIMIT1—Prefetchable Memory Limit Address Register (Device 1)

Address Offset:

26–27h

Default Value:

0000h

Access:

RO, R/W

Size:

16 bits

This register controls the processor to PCI_B prefetchable memory accesses routing based on the

following formula:

PREFETCHABLE_MEMORY_BASE

≤ address ≤ PREFETCHABLE_MEMORY_LIMIT

The upper 12 bits of the register are read/write and correspond to the upper 12 address bits

A[31:20] of the 32-bit address. The bottom four bits of this register are read-only and return zeroes

when read. This register must be initialized by the configuration software. For the purpose of

address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined

memory address range will be at the top of a 1-MB aligned memory block. Note that prefetchable

memory range is supported to allow segregation by the configuration software between the

memory ranges that must be defined as UC and the ones that can be designated as a USWC

(i.e. prefetchable) from the processor perspective.

Bit

Description

15:4

Prefetchable Memory Address Base (PMBASE).

This field corresponds to A[31:20] of the lower

limit of the address range passed by bridge Device 1 across AGP/PCI_B.

3:0

Reserved.

Bit

Description

15:4

Prefetchable Memory Address Limit (PMLIMIT).

This field corresponds to A[31:20] of the upper

limit of the address range passed by bridge Device 1 across AGP/PCI_B.

3:0

Reserved.

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