845GL datasheet(85/193 Pages) INTEL

85 / 193 page

Intel® 82845G/82845GL/82845GV GMCH Datasheet

3.5.2.14

IOBASE1—I/O Base Address Register (Device 1)

Address Offset:

1Ch

Default Value:

F0h

Access:

RO, R/W

Size:

8 bits

This register controls the processor to PCI_B/AGP I/O access routing based on the following

formula:

IO_BASE

≤ address ≤ IO_LIMIT

Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0]

are treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4-KB

boundary.

3.5.2.15

IOLIMIT1—I/O Limit Address Register (Device 1)

Address Offset:

1Dh

Default Value:

00h

Access:

RO, R/W

Size:

8 bits

This register controls the processor to PCI_B/AGP I/O access routing based on the following

formula:

IO_BASE

≤ address ≤ IO_LIMIT

Only the upper four bits are programmable. For the purpose of address decode, address bits

A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of

a 4-KB aligned address block.

Bit

Description

7:4

I/O Address Base (IOBASE).

Corresponds to A[15:12] of the I/O addresses passed by bridge 1 to

AGP/PCI_B.

3:0

Reserved.

Bit

Description

7:4

I/O Address Limit (IOLIMIT).

This field corresponds to A[15:12] of the I/O address limit of Device 1.

Devices between this upper limit and IOBASE1 will be passed to AGP/PCI_B.

3:0

Reserved.

845GL bảng dữ liệu(PDF) 85 Page - Intel Corporation

845GL bảng dữ liệu(HTML) 85 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL