845GL datasheet(98/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

3.5.3.11

MMADR—Memory Mapped Range Address Register (Device 2)

Address Offset:

14–

17h

Default Value:

00000000h

Access:

R/W, RO

Size:

32 bits

This register requests allocation for the IGD registers and instruction ports. The allocation is for

512 KB and the base address is defined by bits [31:19].

3.5.3.12

SVID2—Subsystem Vendor Identification Register (Device 2)

Address Offset:

2C–

2Dh

Default Value:

0000h

Access:

R/WO

Size:

16 bits

3.5.3.13

SID2—Subsystem Identification Register (Device 2)

Address Offset:

2E–

2Fh

Default Value:

0000h

Access:

R/WO

Size:

16 bits

Bit

Description

31:19

Memory Base Address— R/W.

Set by the operating system. These bits correspond to address

signals [31:19].

18:4

Address Mask— RO.

Hardwired to zeros to indicate 512-KB address range.

Prefetchable Memory— RO.

Hardwired to 0 to prevent prefetching.

2:1

Memory Type— RO.

Hardwired to zeros to indicate 32-bit address.

Memory / IO Space— RO.

Hardwired to 0 to indicate memory space.

Bit

Description

15:0

Subsystem Vendor ID.

This value is used to identify the vendor of the subsystem. This register

should be programmed by BIOS during boot-up. Once written, this register becomes read only. This

Bit

Description

15:0

Subsystem Identification.

This value is used to identify a particular subsystem. This field should be

programmed by BIOS during boot-up. Once written, this register becomes read only. This register

can only be cleared by a Reset.

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