845GL datasheet(25/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

Signal Description

2.2

Memory Interface

2.2.1

DDR SDRAM Interface

Signal Name

Type

Description

SCMDCLK_[5:0]

SSTL_2

Differential DDR Clock: SCMDCLK and SCMDCLK# pairs are differential

clock outputs. The crossing of the positive edge of SCMDCLK and the

negative edge of SCMDCLK# is used to sample the address and control

signals on the SDRAM. There are 3 pairs to each DIMM.

SCMDCLK_[5:0]#

SSTL_2

Complementary Differential DDR Clock: These are the complementary

Differential DDR Clock signals.

SCS_[3:0]#

SSTL_2

Chip Select: These signals select particular SDRAM components during

the active state. There is one SCS# for each SDRAM row, toggled on the

positive edge of SCMDCLK.

SMAA_[12:0],

SMAB_[5,4,2,1]

SSTL_2

Memory Address: These signals provide the multiplexed row and column

address to the SDRAM. SMAB_[5,4,2,1] signals are selective CPC signals

and are identical to SMAA_[5,4,2,1].

SBA[1:0]

SSTL_2

Bank Select (Bank Address): These signals define which banks are

selected within each SDRAM row. Bank select and memory address signals

combine to address every possible location within an SDRAM device.

SRAS#

SSTL_2

Row Address Strobe: SRAS# is used with SCAS# and SWE# (along with

SCS#) to define the SDRAM commands.

SCAS#

SSTL_2

Column Address Strobe: SCAS# is used with SRAS# and SWE# (along

with SCS#) to define the SDRAM commands.

SWE#

SSTL_2

Write Enable: SWE# is used with SCAS# and SRAS# (along with SCS#) to

define the SDRAM commands.

SDQ_[63:0]

I/O

SSTL_2

Data Lines: SDQ_[63:0] interface to the SDRAM data bus.

SDM_[7:0]

SSTL_2

Data Mask: When activated during writes, the corresponding data groups in

the SDRAM are masked. There is one SDM for every eight data lines. SDM

can be sampled on both edges of the data strobes.

SDQS_[7:0]

I/O

SSTL_2

Data Strobes: Data strobes are used for capturing data. During writes,

SDQS is centered in data. During reads, SDQS is edge aligned with data.

The following list matches the data strobe with the data bytes.

SDQS_7 = SDQ_[63:56]

SDQS_6 = SDQ_[55:48]

SDQS_5 = SDQ_[47:40]

SDQS_4 = SDQ_[39:32]

SDQS_3 = SDQ_[31:24]

SDQS_2 = SDQ_[23:16]

SDQS_1 = SDQ_[15:8]

SDQS_0 = SDQ_[7:0]

SCKE_[3:0]

SSTL_2

Clock Enable: SCKE is used to initialize DDR SDRAM during power-up and

to place all SDRAM rows into and out of self-refresh during Suspend-to-

RAM. SCKE is also used to dynamically power down inactive SDRAM rows.

There is one SCKE per SDRAM row, toggled on the positive edge of

SCMD_CLK.

SRCVEN_OUT#

SSTL_2

Receive Enable Out: This signal is a feedback testpoint signal used to

enable the DQS input buffers during reads. This pin should be connect to

SRCVEN_IN through an un-populated backside resistor site.

SRCVEN_IN#

SSTL_2

Receive Enable In: This signal is a feedback testpoint signal used to

enable the DQS input buffers during reads.

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