845GL datasheet(84/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

3.5.2.11

SBUSN1—Secondary Bus Number Register (Device 1)

Address Offset:

19h

Default Value:

00h

Access:

R/W

Size:

8 bits

This register identifies the bus number assigned to the second bus side of the “virtual” PCI-to-PCI

bridge (i.e., to PCI_B/AGP). This number is programmed by the PCI configuration software to

allow mapping of configuration cycles to PCI_B/AGP.

3.5.2.12

SUBUSN1—Subordinate Bus Number Register (Device 1)

Address Offset:

1Ah

Default Value:

00h

Access:

R/W

Size:

8 bits

This register identifies the subordinate bus (if any) that resides at the level below PCI_B/AGP. This

number is programmed by the PCI configuration software to allow mapping of configuration

cycles to PCI_B/AGP.

3.5.2.13

SMLT1—Secondary Bus Master Latency Timer Register (Device 1)

Address Offset:

1Bh

Default Value:

00h

Access:

RO, R/W

Size:

8 bits

This register control the bus tenure of the GMCH on AGP/PCI the same way Device 0 MLT

controls the access to the PCI_A bus.

Bit

Description

7:0

Secondary Bus Number (BUSN).

This field is programmed by configuration software with the bus

number assigned to PCI_B.

Bit

Description

7:0

Subordinate Bus Number (BUSN).

This register is programmed by configuration software with the

number of the highest subordinate bus that lies behind the Device 1 bridge. When only a single PCI

device resides on the AGP/PCI_B segment, this register will contain the same value as the SBUSN1

Bit

Description

7:3

Secondary MLT Counter Value (MLT).

Programmable, default = 0 (SMLT disabled)

2:0

Reserved.

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