845GL datasheet(44/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

3.3.1

Standard PCI Bus Configuration Mechanism

The PCI Local Bus Specification, Revision 2.1 defines a slot based “configuration space” that

allows each device to contain up to eight functions with each function containing up to 256, 8-bit

configuration registers. The PCI Local Bus Specification, Revision 2.1 defines two bus cycles to

access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O

spaces are supported directly by the processor. Configuration space is supported by a mapping

mechanism implemented within the GMCH. The PCI Local Bus Specification, Revision 2.2 defines

the Configuration Mechanism to access configuration space.

The configuration access mechanism makes use of the CONFIG_ADDRESS Register (at I/O

address 0CF8h though 0CFBh) and CONFIG_DATA Register (at I/O address 0CFCh though

0CFFh). To reference a configuration register a DWord I/O write cycle is used to place a value into

CONFIG_ADDRESS that specifies the PCI bus, the device on that bus, the function within the

device, and a specific configuration register of the device function being accessed.

CONFIG_ADDRESS[31] must be 1 to enable a configuration cycle. CONFIG_DATA then

becomes a window into the four bytes of configuration space specified by the contents of

CONFIG_ADDRESS. Any read or write to CONFIG_DATA will result in the GMCH translating

the CONFIG_ADDRESS into the appropriate configuration cycle.

The GMCH is responsible for translating and routing the processor’s I/O accesses to the

CONFIG_ADDRESS and CONFIG_DATA registers to internal GMCH configuration registers,

Hub Interface or AGP/PCI_B.

3.3.2

PCI Bus #0 Configuration Mechanism

The GMCH decodes the Bus Number (bits 23:16) and the Device Number fields of the

CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the

configuration cycle is targeting a PCI Bus #0 device. The Host-HI Bridge entity within the GMCH

is hardwired as Device 0 on PCI Bus #0. The Host-AGP/PCI_B Bridge entity within the GMCH is

hardwired as Device 1 on PCI Bus #0. The integrated Graphics entity within the GMCH is

hardwired as Device 2 on PCI Bus #0. Configuration cycles to any of the GMCH’s internal devices

are confined to the GMCH and not sent over the hub interface.

3.3.3

Primary PCI and Downstream Configuration Mechanism

If the Bus Number in the CONFIG_ADDRESS is non-zero, and is less than the value in the Host-

AGP/PCI_B device’s Secondary Bus Number register or greater than the value in the Host-AGP/

PCI_B device’s Subordinate Bus Number register, the GMCH will generate a Type 1 Hub Interface

Configuration Cycle.

If the cycle is forwarded to the ICH4 via the hub interface, the ICH4 compares the non-zero Bus

Number with the Secondary Bus Number and Subordinate Bus Number registers of its PCI-to-PCI

bridges to determine if the configuration cycle is meant for Primary PCI, or a downstream PCI bus.

3.3.4

AGP/PCI_B Bus Configuration Mechanism

From the chipset configuration perspective, AGP/PCI_B is seen as PCI bus interfaces residing on a

Secondary Bus side of the “virtual” PCI-to-PCI bridges referred to as the GMCH Host-PCI_B/

AGP bridge. On the Primary bus side, the “virtual” PCI-to-PCI bridge is attached to PCI Bus #0.

Therefore, the Primary Bus Number register is hardwired to 0. The “virtual” PCI-to-PCI bridge

entity converts Type #1 PCI Bus Configuration cycles on PCI Bus #0 into Type 0 or Type 1

configuration cycles on the AGP/PCI_B interface. Type 1 configuration cycles on PCI Bus #0 that

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