845GL datasheet(113/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

113

Functional Description

4.3.1.3

AGP Transaction Ordering

The GMCH observes transaction ordering rules as defined by the Accelerated Graphics Port

Interface Specification, Revision 2.0. The GMCH implements read after write hazard protection for

normal priority commands through the use of a “pseudo FENCE.” When a normal priority read

command is placed in the command queue, it is checked for possible conflicts with any normal

priority write commands that have been received but not yet delivered to SDRAM. If a potential

conflict is detected, the GMCH inserts a FENCE between the read and all previous normal priority

commands in the queue. This ensures that any normal priority write that was received prior to the

read will be pushed to SDRAM before the read is serviced. As a result the read will be guaranteed

to receive the new data when it is serviced. Note that all reads received prior to the read that

potentially conflicts will also be serviced prior to the conflicting read.

High priority reads and writes are not checked for conflicts between themselves or normal priority

reads and writes. AGP commands (delivered via PIPE# or SBA, not FRAME#) snoop the global

SDRAM write buffer.

4.3.1.4

AGP Electrical Characteristics

The 4X data transfers use 1.5 V signaling levels as described in the Accelerated Graphics Port

Interface Specification, Revision 2.0. The GMCH supports 1X/2X/PCI data transfers using 1.5 V

signaling levels. The following table shows the data rates and signaling levels supported by the

GMCH:

4.3.1.5

Support for PCI-66 Devices

The GMCH’s AGP interface can be used as a PCI-66 MHz interface with the following

restrictions:

• Support for 1.5 V operation only.

• Support for only one device. GMCH does not provide arbitration or electrical support for more

than one PCI-66 device.

• The PCI-66 device must meet the Accelerated Graphics Port Interface Specification, Revision

2.0.

• The GMCH does not provide full PCI-to-PCI bridge support between AGP/PCI and hub

interface. Traffic between AGP and hub interface is limited to hub interface-to-AGP memory

writes.

• LOCK# signal is not present. Neither inbound nor outbound locks are supported.

• SERR#/PERR# signals are not present.

• 16 clock Subsequent Data Latency timer (instead of 8).

Data Rate

Signaling Level

1.5 V

3.3 V

PCI-66

Yes

1X AGP

Yes

2X AGP

Yes

4X AGP

Yes

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