845GL datasheet(110/193 Pages) INTEL

110 / 193 page

Functional Description

110

Intel® 82845G/82845GL/82845GV GMCH Datasheet

4.2.5

DRAM Performance Description

The overall memory performance is controlled by the DRAM timing register, pipelining depth used

in the GMCH, memory speed grade, and the type of SDRAM used in the system. In addition, the

exact performance in a system is also dependent on the total memory supported, external buffering,

and memory array layout. The most important contribution to overall performance by the system

memory controller is to minimize the latency required to initiate and complete requests to memory,

and to support the highest possible bandwidth (full streaming, quick turnarounds). One measure of

performance is the total flight time to complete a cache line request. A true discussion of

performance involves the entire chipset, not just the system memory controller.

Table 4-5. Address Translation and Decoding

1 Meg

x 16

x 4 bks

x 8

x 2

[26]

2 Meg

x 8

x 4 bks

x 9

x 2

[26]

128

2 Meg

x 16

x 4 bks

x 9

x 2

[26]

256

4 Meg

x 16

x 4 bks

128

x 9

x 2

128

4 Meg

x 8

x 4 bks

128

x 10

x 2

[27]

256

8 Meg

x 8

x 4 bks

256

x 10

x 2

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