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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DM505LRBABF bảng dữ liệu(PDF) 14 Page - Texas Instruments |
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DM505LRBABF bảng dữ liệu(HTML) 14 Page - Texas Instruments |
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14 / 290 page  Copyright © 2016–2017, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback 14 DM505 SPRS976D – NOVEMBER 2016 – REVISED JULY 2017 www.ti.com Table 4-1. Pin Attributes(1) (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] BALL RESET REL. MUXMODE [8] I/O VOLTAGE VALUE [9] POWER [10] HYS [11] BUFFER TYPE [12] PULL UP/DOWN TYPE [13] DSIS [14] AA3 ddr1_d16 ddr1_d16 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy AA2 ddr1_d17 ddr1_d17 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy Y3 ddr1_d18 ddr1_d18 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy V2 ddr1_d19 ddr1_d19 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy U3 ddr1_d20 ddr1_d20 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy V3 ddr1_d21 ddr1_d21 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy Y2 ddr1_d22 ddr1_d22 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy Y1 ddr1_d23 ddr1_d23 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy U21 ddr1_d24 ddr1_d24 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy T20 ddr1_d25 ddr1_d25 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy R21 ddr1_d26 ddr1_d26 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy U20 ddr1_d27 ddr1_d27 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy R22 ddr1_d28 ddr1_d28 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy V20 ddr1_d29 ddr1_d29 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy W22 ddr1_d30 ddr1_d30 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy U22 ddr1_d31 ddr1_d31 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy AB8 ddr1_dqm0 ddr1_dqm0 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy Y18 ddr1_dqm1 ddr1_dqm1 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy AB3 ddr1_dqm2 ddr1_dqm2 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy W21 ddr1_dqm3 ddr1_dqm3 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy AA5 ddr1_dqs0 ddr1_dqs0 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy AA20 ddr1_dqs1 ddr1_dqs1 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy W1 ddr1_dqs2 ddr1_dqs2 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy |
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