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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DM505LRBABF bảng dữ liệu(PDF) 12 Page - Texas Instruments |
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DM505LRBABF bảng dữ liệu(HTML) 12 Page - Texas Instruments |
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12 / 290 page  Copyright © 2016–2017, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback 12 DM505 SPRS976D – NOVEMBER 2016 – REVISED JULY 2017 www.ti.com Table 4-1. Pin Attributes(1) (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] BALL RESET REL. MUXMODE [8] I/O VOLTAGE VALUE [9] POWER [10] HYS [11] BUFFER TYPE [12] PULL UP/DOWN TYPE [13] DSIS [14] F2 ddr1_casn ddr1_casn 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS DDR PUx/PDy G1 ddr1_ck ddr1_ck 0 O PD drive clk (OFF) 0 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS DDR PUx/PDy AB13 ddr1_dqm_ecc ddr1_dqm_ecc 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy AB10 ddr1_dqsn_ecc ddr1_dqsn_ecc 0 IO PU PU 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy AA10 ddr1_dqs_ecc ddr1_dqs_ecc 0 IO PD PD 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy G2 ddr1_nck ddr1_nck 0 O PD drive clk (OFF) 0 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS DDR PUx/PDy F1 ddr1_rasn ddr1_rasn 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS DDR PUx/PDy N1 ddr1_rst ddr1_rst 0 O PD drive 0 (OFF) 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy E3 ddr1_wen ddr1_wen 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS DDR PUx/PDy U4 ddr1_a0 ddr1_a0 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy C1 ddr1_a1 ddr1_a1 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS DDR PUx/PDy D3 ddr1_a2 ddr1_a2 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS DDR PUx/PDy R4 ddr1_a3 ddr1_a3 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy T4 ddr1_a4 ddr1_a4 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy N3 ddr1_a5 ddr1_a5 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy T2 ddr1_a6 ddr1_a6 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy N2 ddr1_a7 ddr1_a7 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy T1 ddr1_a8 ddr1_a8 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy U1 ddr1_a9 ddr1_a9 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy D1 ddr1_a10 ddr1_a10 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS DDR PUx/PDy R3 ddr1_a11 ddr1_a11 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy U2 ddr1_a12 ddr1_a12 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy C3 ddr1_a13 ddr1_a13 0 O PD drive 1 (OFF) 0 1.35/1.5/1.8 vdds_ddr2 NA LVCMOS DDR PUx/PDy |
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