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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DM505LRBABF bảng dữ liệu(PDF) 95 Page - Texas Instruments |
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DM505LRBABF bảng dữ liệu(HTML) 95 Page - Texas Instruments |
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95 / 290 page  95 DM505 www.ti.com SPRS976D – NOVEMBER 2016 – REVISED JULY 2017 Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated Table 5-12. Dual Voltage LVCMOS DC Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER DESCRIPTION MIN NOM MAX UNIT 1.8-V Mode VIH Input high-level threshold 0.65*VDDS V VIL Input low-level threshold 0.35*VDDS V VHYS Input hysteresis voltage 100 mV VOH Output high-level threshold (IOH = 2 mA) VDDS-0.45 V VOL Output low-level threshold (IOL = 2 mA) 0.45 V IDRIVE Pin Drive strength at PAD Voltage = 0.45V or VDDS- 0.45V 6 mA IIN Input current at each I/O pin 16 µA IOZ IOZ(IPAD Current) at each IO pin. PAD is swept from 0 to VDDS and the Max(I(PAD)) is measured and is reported as IOZ 11.5 µA IIN with pulldown enabled Input current at each I/O pin with weak pulldown enabled measured when PAD = VDDS 60 120 200 µA IIN with pullup enabled Input current at each I/O pin with weak pullup enabled measured when PAD = 0 60 120 210 µA CPAD Pad capacitance (including package capacitance) 4 pF ZO Output impedance (drive strength) 40 Ω 3.3-V Mode VIH Input high-level threshold 2 V VIL Input low-level threshold 0.8 V VHYS Input hysteresis voltage 200 mV VOH Output high-level threshold (IOH =100µA) VDDS-0.2 V VOL Output low-level threshold (IOL = 100µA) 0.2 V IDRIVE Pin Drive strength at PAD Voltage = 0.45V or VDDS- 0.45V 6 mA IIN Input current at each I/O pin 64 µA IOZ IOZ(IPAD Current) at each IO pin. PAD is swept from 0 to VDDS and the Max(I(PAD)) is measured and is reported as IOZ 64 µA IIN with pulldown enabled Input current at each I/O pin with weak pulldown enabled measured when PAD = VDDS 10 100 290 µA IIN with pullup enabled Input current at each I/O pin with weak pullup enabled measured when PAD = 0 40 100 200 µA CPAD Pad capacitance (including package capacitance) 4 pF ZO Output impedance (drive strength) 40 Ω (1) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Table 4-1, POWER [10] column. Table 5-13. Analog-to-Digital ADC Subsystem Electrical Specifications over operating free-air temperature range (unless otherwise noted) PARAMETER CONDITIONS MIN NOM MAX UNIT Analog Input Full-scale Input Range adc_vrefp V Vref Should be less than or equal to vdds_18v. 1.62 vdds_18v V Differential Non-Linearity (DNL) -1 1 LSB Integral Non-Linearity (INL) adc_vrefp = vdds_18v ±2 LSB Gain Error adc_vrefp = vdds_18v ±4 LSB Offset Error adc_vrefp = vdds_18v ±3 LSB |
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