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MPC5744P bảng dữ liệu(PDF) 90 Page - Freescale Semiconductor, Inc |
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MPC5744P bảng dữ liệu(HTML) 90 Page - Freescale Semiconductor, Inc |
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90 / 114 page ![]() MPC5744P Data Sheet, Rev. 0.3 Preliminary—Subject to Change Without Notice Electrical characteristics Freescale Semiconductor 90 3.17.2 WKUP/NMI timing 3.17.3 Debug/JTAG/Nexus/Aurora timing 3.17.3.1 JTAG interface timing NOTES: 1 V DD_HV_IOx = 3.3 V -5%,+10%, TJ = –40 / 165 °C, unless otherwise specified 2 All values need to be confirmed during device validation. 3 Data based on characterization results, not tested in production Table 39. WKUP/NMI glitch filter No. Symbol Parameter Min Typ Max Unit 1WFNMI D NMI pulse width that is rejected — — 20 ns 2WNFNMI D NMI pulse width that is passed 400 — — ns Table 40. JTAG pin AC electrical characteristics1 NOTES: 1 These specifications apply to JTAG boundary scan only. # Symbol C Characteristic Min Max Unit 1tJCYC CC D TCK Cycle Time2 36 — ns 2tJDC CC T TCK Clock Pulse Width 40 60 % 3tTCKRISE CC D TCK Rise and Fall Times (40% - 70%) — 3 ns 4tTMSS, tTDIS CC D TMS, TDI Data Setup Time 5 — ns 5tTMSH, tTDIH CC D TMS, TDI Data Hold Time 5 — ns 6tTDOV CC D TCK Low to TDO Data Valid — 153 ns 7tTDOI CC C TCK Low to TDO Data Invalid 0 — ns 8tTDOHZ CC D TCK Low to TDO High Impedance — 15 ns 9tJCMPPW CC D JCOMP Assertion Time 100 — ns 10 tJCMPS CC D JCOMP Setup Time to TCK Low 40 — ns 11 tBSDV CC D TCK Falling Edge to Output Valid — 6004 ns 12 tBSDVZ CC D TCK Falling Edge to Output Valid out of High Impedance — 600 ns 13 tBSDHZ CC D TCK Falling Edge to Output High Impedance — 600 ns 14 tBSDST CC D Boundary Scan Input Valid to TCK Rising Edge 15 — ns 15 tBSDHT CC D TCK Rising Edge to Boundary Scan Input Invalid 15 — ns |
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