HT46R0664 datasheet(48/92 Pages) HOLTEK

48 / 92 page

Rev. 1.00

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Rev. 1.00

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HT46R0664

Enhanced A/D+LCD Type 8-Bit OTP MCU

Bit 2~0

T0PS2, T0PS1, T0PS0: Timer prescaler rate selection Timer internal clock

000: fTP

001: fTP/2

010: fTP/4

011: fTP/8

100: fTP/16

101: fTP/32

110: fTP/64

111: fTP/128

TMR1C Register

Bit

Name

T1M1

T1M0

T1S

T1ON

T1EG

—

R/W

—

POR

—

Bit 7,6

T1M1, T1M0: Timer 1 operation mode selection

00: no mode available

01: event counter mode

10: timer mode

11: pulse width capture mode

Bit 5

T1S: Timer clock source

0: fSYS/4

1: LXT Oscillator

Bit 4

T1ON: Timer/event counter counting enable

0: disable

1: enable

Bit 3

T1EG: Event counter active edge selection

1: count on falling edge

0: count on rising edge

Pulse Width Capture active edge selection

1: start counting on rising edge, stop on falling edge

0: start counting on falling edge, stop on rising edge

Bit 2~0

Unimplemented, read as “0”

Timer Mode

In this mode, the Timer/Event Counter can be utilised to measure fixed time intervals, providing

an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode,

the Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the

correct value as shown.

Control Register Operating Mode Select Bits for the Timer Mode.

Bit7

Bit6

In this mode the internal clock is used as the timer clock. The timer input clock source is fSYS, fSYS/4,

PFD0 or the LXT oscillator. However, this timer clock source is further divided by a prescaler, the

value of which is determined by the bits T0PS2~T0PS0 in the Timer Control Register. The timer-on

bit, TnON must be set high to enable the timer to run. Each time an internal clock high to low

transition occurs, the timer increments by one. When the timer is full and overflows, an interrupt

sigal is generated and the timer will reload the value already loaded into the preload register and

continue counting. A timer overflow condition and corresponding internal interrupts are two of the

wake-up sources. However, the internal interrupts can be disabled by ensuring that the TnE bits of

the INTC0 register are reset to zero.

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